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    PROCESS OF AN EMBEDDED COMPONENT STRUCTURE
    73.
    发明申请
    PROCESS OF AN EMBEDDED COMPONENT STRUCTURE 审中-公开
    嵌入式组件结构的过程

    公开(公告)号：US20160255751A1

    公开(公告)日：2016-09-01

    申请号：US15152564

    申请日：2016-05-12

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Wei-Ming Cheng

    IPC: H05K13/04 ,  H05K1/18 ,  H05K1/11 ,  H05K3/28

    CPC classification number: H05K13/04 ,  H05K1/11 ,  H05K1/114 ,  H05K1/183 ,  H05K1/184 ,  H05K1/186 ,  H05K3/284 ,  H05K2201/09072 ,  H05K2201/10083 ,  H05K2201/10121 ,  H05K2201/10151

    Abstract: A wiring board is provided, wherein electrical function of the wiring board is normal, the wiring board has a front side, a reverse side opposite to the front side, an opening and an interconnection layer, the opening penetrates the wiring board and connects the front side and the reverse side, and the interconnection layer is located on the front side and extends toward the opening. A component is bonded to the wiring board, wherein electrical function of the component is normal, the component has an active surface, a back surface opposite to the active surface, and a working area located on the active surface, the active surface is bonded to the interconnection layer, the component is located in the opening, and the active surface and the front side of the wiring board face in a same direction. An encapsulant is filled into the opening, so as to cover the component and expose the working area.

    Abstract translation: 提供一种布线板，其中布线板的电气功能正常，布线板具有正面，与正面相反的背面，开口和互连层，开口穿透布线板并连接前面 侧面和背面，并且互连层位于前侧并且朝向开口延伸。 部件被接合到布线板上，其中部件的电功能是正常的，部件具有活性表面，与有效表面相对的后表面以及位于活性表面上的工作区域，活性表面被粘合到 互连层，部件位于开口中，并且布线板的有源面和正面朝向相同的方向。 将密封剂填充到开口中，以覆盖部件并暴露工作区域。

    METHOD OF FABRICATING AN ELECTRICAL DEVICE PACKAGE STRUCTURE
    74.
    发明申请
    METHOD OF FABRICATING AN ELECTRICAL DEVICE PACKAGE STRUCTURE 审中-公开
    制造电气设备包装结构的方法

    公开(公告)号：US20160007472A1

    公开(公告)日：2016-01-07

    申请号：US14855404

    申请日：2015-09-16

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

    IPC: H05K3/00 ,  H05K3/42 ,  H05K3/06 ,  H05K3/30

    CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is foamed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

    Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中第一凹陷图案通过第一导电图案在介电层中发泡。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。

    Electrical device package structure and method of fabricating the same
    75.
    发明授权
    Electrical device package structure and method of fabricating the same 有权
    电器件封装结构及其制造方法

    公开(公告)号：US09161454B2

    公开(公告)日：2015-10-13

    申请号：US13726230

    申请日：2012-12-24

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

    IPC: H05K1/16 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/00 ,  H05K3/46

    CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.

    Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。

    INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF
    76.
    发明申请
    INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    嵌入式基板及其制造方法

    公开(公告)号：US20140138142A1

    公开(公告)日：2014-05-22

    申请号：US14164245

    申请日：2014-01-26

    Applicant: UNIMICRON TECHNOLOGY CORP.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H05K3/10 ,  H05K1/11

    CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

    CIRCUIT BOARD
    77.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20140034361A1

    公开(公告)日：2014-02-06

    申请号：US14052468

    申请日：2013-10-11

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

    IPC: H05K1/11 ,  H05K1/02

    CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/107 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.

    Abstract translation: 提供了包括电路基板，电介质层，第一导电层和第二导电层的电路板。 电路基板具有第一表面和第一电路层。 电介质层设置在电路基板上并覆盖第一表面和第一电路层。 电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔和凹版图案。 第一导电层设置在盲孔内。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层通过第一导电层与第一电路层电连接。

    Circuit substrate structure and manufacturing method thereof
    78.
    发明授权
    Circuit substrate structure and manufacturing method thereof 有权

    公开(公告)号：US12243838B2

    公开(公告)日：2025-03-04

    申请号：US17567883

    申请日：2022-01-04

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

    PACKAGE STRUCTURE
    79.
    发明公开
    PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20240248264A1

    公开(公告)日：2024-07-25

    申请号：US18623035

    申请日：2024-04-01

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

    IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

    CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

    Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

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