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    Mems device having support structure to reduce distortion due to stress to a minimum, and manufacturing method thereof
    73.
    发明专利
    Mems device having support structure to reduce distortion due to stress to a minimum, and manufacturing method thereof 审中-公开
    具有支持结构以减少因最小应力而产生的失效的MEMS器件及其制造方法

    公开(公告)号：JP2013068959A

    公开(公告)日：2013-04-18

    申请号：JP2012251991

    申请日：2012-11-16

    Applicant: Qualcomm Mems Technologies Inc ,  クォルコム・メムズ・テクノロジーズ・インコーポレーテッド

    Inventor： LIOR KOGUT ,  ZHONG FAN

    IPC: G02B26/02 ,  B81B3/00 ,  B81C1/00

    CPC classification number: G02B26/0841 ,  B81B3/0072 ,  B81B2201/047 ,  B81B2203/0163 ,  B81B2203/019 ,  B81B2203/0307 ,  B81B2203/053 ,  B81C1/00142 ,  B81C1/00666 ,  B81C2201/0167 ,  G02B26/001 ,  Y10S359/90

    Abstract: PROBLEM TO BE SOLVED: To provide a MEMS device having a support structure to reduce distortion due to stress to a minimum, and a manufacturing method thereof.SOLUTION: The embodiment of a MENS device includes a movable layer supported by an upper support structure and may further include a lower support structure. In an embodiment, the residual stress in the upper support structure and the residual stress in the movable layer are substantially equal. In another embodiment, the residual stress in the upper support structure and the residual stress in the lower support structure are substantially equal. In a specific embodiment, the substantially equal residual stress is obtained through the use of a layer formed of the same material with the same thickness. In a further embodiment, the substantially equal residual stress is obtained through the use of a support structure and/or a movable layer having a mirror image from each other.

    Abstract translation: 要解决的问题：提供一种具有支撑结构的MEMS器件，以将由于应力引起的变形减小至最小，及其制造方法。 解决方案：MENS装置的实施例包括由上支撑结构支撑的可移动层，并且还可以包括下支撑结构。 在一个实施例中，上支撑结构中的残余应力和可移动层中的残余应力基本相等。 在另一个实施例中，上支撑结构中的残余应力和下支撑结构中的残余应力基本相等。 在具体实施例中，通过使用由具有相同厚度的相同材料形成的层获得基本上相等的残余应力。 在另一实施例中，通过使用具有彼此具有镜像的支撑结构和/或可移动层来获得基本相等的残余应力。 版权所有（C）2013，JPO＆INPIT

    Electron beam mask, substrate therefor, and electron beam mask blank
    75.
    发明专利
    Electron beam mask, substrate therefor, and electron beam mask blank 有权
    电子束屏蔽，其基板和电子束屏蔽层

    公开(公告)号：JP2003338449A

    公开(公告)日：2003-11-28

    申请号：JP2002146882

    申请日：2002-05-21

    Applicant: Hoya Corp ,  Hoya株式会社

    Inventor： AMAMIYA ISAO

    IPC: B81B3/00 ,  G03F1/20 ,  G03F1/68 ,  G03F1/80 ,  H01L21/027 ,  G03F1/16

    CPC classification number: B81C1/00666 ,  B81C2201/0167 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01J2237/31794

    Abstract: PROBLEM TO BE SOLVED: To provide a substrate for an electron beam mask capable of improving the tolerance in manufacturing an electron beam mask.
    SOLUTION: The substrate for an electron beam mask is provided with a substrate of a material containing silicon for forming a support body which supports a thin film layer by a rear-surface etching, an etching stopper layer formed on the substrate, and the thin film layer of the material containing the silicon formed on the etching stopper layer. The etching stopper layer is made from, for example, a metal compound (for example, chrome nitride (CrNX)).
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供一种能够提高制造电子束掩模的公差的电子束掩模用基板。 ＆lt; P＆gt;解决方案：电子束掩模用基板设置有含有硅的材料的基板，用于形成支撑体，通过后表面蚀刻来支撑薄膜层，形成在基板上的蚀刻停止层，以及 含有形成在蚀刻停止层上的硅的材料的薄膜层。 蚀刻停止层由例如金属化合物（例如，氮化铬（CrNX））制成。 版权所有（C）2004，JPO

    전자선 마스크용 기판, 전자선 마스크 블랭크, 및 전자선마스크
    78.
    发明公开
    전자선 마스크용 기판, 전자선 마스크 블랭크, 및 전자선마스크 失效
    用于电子束掩模的基底，电子束掩模坯和电子束掩模

    公开(公告)号：KR1020030091731A

    公开(公告)日：2003-12-03

    申请号：KR1020030032356

    申请日：2003-05-21

    Applicant: 호야 가부시키가이샤

    Inventor： 아메미야,이사오

    IPC: H01L21/027

    CPC classification number: B81C1/00666 ,  B81C2201/0167 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01J2237/31794

    Abstract: 본 발명은 전자선 마스크 제작의 여유도를 현저하게 향상시킬 수 있는 전자선 마스크용 기판 등을 제공하는 것을 목적으로 한다. 이면 에칭 가공에 의해 박막층을 지지하기 위한 지지체를 형성하기 위한 실리콘을 포함하는 재료로 이루어지는 기판과, 이 기판 상에 형성된 에칭 스토퍼층과, 이 에칭 스토퍼층 상에 형성된 실리콘을 포함하는 재료로 이루어지는 박막층을 가지는 전자선 마스크용 기판으로서, 상기 에칭 스토퍼층이, 예를 들면 금속 화합물(예를 들면 질화 크롬(CrN
    X ) 등)인 것을 특징으로 한다.

    DETACHABLE MICRO- AND NANO-COMPONENTS FOR A SPACE-SAVING USE
    79.
    发明申请
    DETACHABLE MICRO- AND NANO-COMPONENTS FOR A SPACE-SAVING USE 审中-公开
    移动微纳米组件节省空间的应用

    公开(公告)号：WO2012113902A2

    公开(公告)日：2012-08-30

    申请号：PCT/EP2012053147

    申请日：2012-02-24

    Applicant: HARTING KGAA ,  GATZEN PROF DR-ING HANS-HEINRICH ,  GRIESBACH DIPL-ING TIM

    Inventor： GATZEN PROF DR-ING HANS-HEINRICH ,  GRIESBACH DIPL-ING TIM

    IPC: B81B3/00

    CPC classification number: H05K1/0271 ,  B81B3/0072 ,  B81B2201/11 ,  B81C2201/0167 ,  H05K3/303 ,  Y10T29/49133

    Abstract: The invention relates to space-saving micro- and nano-components and to methods for producing same. The components are characterized in that they do not comprise a rigid substrate having a considerable thickness. The mechanical stresses, which result in deformations and/or warpage within a component, are compensated by means of a mechanically stress-compensated design and/or by means of active mechanical stress compensation by depositing suitable stress compensation layers such that there is no need for relatively thick substrates. Thus, the overall thickness of the components is decreased and the integration options thereof in technical systems are improved. In addition, the field of application of such components is expanded.

    Abstract translation: 根据本发明，节省空间的微和纳米组件和方法，提出了它们的制备。 这些部件的特征在于不具有相当厚度的刚性衬底。 在此，变形和/或扭曲的机械应力补偿体的装置在部件内引起的机械应力和/或将要通过有源机械应力补偿装置通过沉积合适的电压补偿层，使得没有Bedarfnach是相对厚的基材补偿。 因此，组分的总厚度减少及其Integrationsmöglichkeitin改进的技术系统。 此外，这些组件的应用领域也在扩大。

    MULTI-LAYER SUBSTRATE STRUCTURE AND MANUFACTURING METHOD FOR THE SAME
    80.
    发明申请
    MULTI-LAYER SUBSTRATE STRUCTURE AND MANUFACTURING METHOD FOR THE SAME 审中-公开
    多层基板结构及其制造方法

    公开(公告)号：WO2011161318A1

    公开(公告)日：2011-12-29

    申请号：PCT/FI2011/050595

    申请日：2011-06-21

    Applicant: Teknologian tutkimuskeskus VTT ,  PUURUNEN, Riikka ,  HENTTINEN, Kimmo ,  KATTELUS, Hannu ,  SUNI, Tommi

    Inventor： PUURUNEN, Riikka ,  HENTTINEN, Kimmo ,  KATTELUS, Hannu ,  SUNI, Tommi

    IPC: H01L21/02 ,  B81C1/00 ,  C23C16/455

    CPC classification number: H01L21/0228 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/0167 ,  B81C2201/053 ,  B81C2203/0118 ,  H01L29/02

    Abstract: A method for manufacturing a multi-layer substrate structure such as a CSOI wafer structure (cavity-SOI, silicon-on-insulator) comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (302, 404), forming a cavity on the bond side of the first wafer (306, 406), depositing, preferably by ALD (Atomic Layer Deposition), a material layer, such as thin alumina layer, on either wafer arranged so as to at least in places face the other wafer and cover at least portion of the cavity of the first wafer, such as bottom, wall and/or edge thereof, and enable stopping etching, such as dry etching, into the underlying material (308, 408), and bonding the wafers provided with at least the aforesaid ALD layer as an intermediate layer together to form the multi-layer semi- conductor substrate structure (310, 312).A related multi-layer substrate structure is presented.

    Abstract translation: 一种用于制造诸如CSOI晶片结构（空腔SOI，绝缘体上硅）的多层衬底结构的方法，包括获得诸如两个硅晶片的第一和第二晶片，其中至少一个晶片可以是 可选地设置有诸如氧化物层（302,404）的材料层，在第一晶片（306,406）的接合侧上形成空腔，优选通过ALD（原子层沉积）沉积材料层，例如 作为薄氧化铝层，在任一晶片上布置成至少在面对另一晶片的位置并且覆盖第一晶片的空腔的至少一部分，例如底部，壁和/或边缘，并且能够停止蚀刻，例如 作为干蚀刻，进入下层材料（308,408），并将至少提供有上述ALD层的晶片作为中间层结合在一起以形成多层半导体衬底结构（310,312）。 提出了多层基板结构。

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