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    Method of forming a monolayer of particles having at least two different sizes, and products formed thereby
    71.
    发明授权
    Method of forming a monolayer of particles having at least two different sizes, and products formed thereby 失效
    形成具有至少两种不同尺寸的颗粒的单层的方法，以及由此形成的产品

    公开(公告)号：US06977025B2

    公开(公告)日：2005-12-20

    申请号：US10388441

    申请日：2003-03-17

    Applicant: Ciaran Bernard McArdle ,  Rory Brian Barnes

    Inventor： Ciaran Bernard McArdle ,  Rory Brian Barnes

    IPC: G03F7/34 ,  H01R4/04 ,  H05K3/32 ,  B32B31/00

    CPC classification number: H01R4/04 ,  G03F7/34 ,  H01L2224/293 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K3/323 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0769 ,  H05K2203/104 ,  Y10T428/24802 ,  H01L2924/00

    Abstract: The invention provides a method of forming a monolayer of substantive particles including the steps of applying to a substrate a curable composition having substantive particles contained therein, the substantive particles having a particle size on at least one dimension thereof of at least 1 micrometer and being in two or more groups of different sizes; exposing the substantive particle-containing curable composition to a source of energy suitable for effecting polymerization of the curable composition for a sufficient time to effect polymerization of a layer of the curable composition having a thickness of no more than 50% of the height of the largest substantive particles; and optionally, removing uncured curable composition. The invention also provides a method of forming a monolayer of substantive particles in a non-random array where the curable composition comprises a ferrofluid composition. The latter method further comprises the step of subjecting the particle-containing curable ferrofluid composition to a magnetic field for a sufficient time to array the particles in a non-random manner in the composition prior to the exposure.

    Abstract translation: 本发明提供了一种形成单层实质性颗粒的方法，包括以下步骤：将具有其中所含的实质性颗粒的可固化组合物施用于基材，所述实体颗粒的至少一个尺寸的颗粒尺寸至少为1微米， 两组或两组以上不同大小; 将含有实质的含颗粒的可固化组合物暴露于适于实现可固化组合物聚合足够时间的能量源，以实现可固化组合物层的厚度不超过最大厚度的50％ 实质粒子 并且任选地，除去未固化的可固化组合物。 本发明还提供了以非随机阵列形成单层实质性颗粒的方法，其中可固化组合物包含铁磁流体组合物。 后一种方法还包括以下步骤：使含有颗粒的可固化铁磁体组合物经历足够的时间以在曝光之前以非随机方式将组合物排列在组合物中。

    Circuit boards containing vias and methods for producing same
    73.
    发明申请
    Circuit boards containing vias and methods for producing same 有权
    含有通孔的电路板及其制造方法

    公开(公告)号：US20030067074A1

    公开(公告)日：2003-04-10

    申请号：US09974947

    申请日：2001-10-10

    Inventor： Larry D. Kinsman

    IPC: H01L023/52

    CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

    Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

    Abstract translation: 本发明涉及一种用于连接放置在电路板的相对侧上的集成电路的装置和方法，该集成电路通过利用嵌入电路板中的导电元件并从板的一个表面延伸到另一个表面。 导电迹线沿着电路板的表面从导电元件延伸到集成电路。 导电迹线可以由多个导电层形成。

    Electrical interconnect device with customizeable surface layer and interwoven signal lines
    76.
    发明授权
    Electrical interconnect device with customizeable surface layer and interwoven signal lines 失效
    具有可定制表面层和交织信号线的电气互连装置

    公开(公告)号：US5544018A

    公开(公告)日：1996-08-06

    申请号：US227315

    申请日：1994-04-13

    Applicant: Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

    Inventor： Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

    IPC: H01L23/538 ,  H05K1/00 ,  H05K3/46 ,  H05K1/11

    CPC classification number: H01L23/5382 ,  H05K1/0287 ,  H05K1/029 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K1/0298 ,  H05K2201/09345 ,  H05K2201/09945 ,  H05K2203/175 ,  H05K3/467

    Abstract: Provided is an electrical interconnect cell intermittently spaced across a substrate to form an interconnect device or structure. The interconnect device is fully customizable or programmable upon the upper surface to accommodate various electrical components and connectivity to those components. The electrical interconnect device includes a plurality of intermittently spaced first pairs of upper and lower signal lines interwoven with a plurality of intermittently spaced second pairs of upper and lower signal lines. A bonding pad is arranged between adjacent upper and lower signal line pairs and can be connected thereto with conductive links placed upon the surface layer. Each bonding pad includes one or more pad vias which extend perpendicular to the upper surface to conductive structures arranged in lower layers. Approximately one-half of the array of bonding pads are connected to potential conductors. The pairs of upper signal lines can not only be linked, but also can be cut to form a more direct routing between target locations. Moreover, the upper and lower signal lines are connected in order for traces to extend across the entire interconnect structure for ease of testability.

    Abstract translation: 提供了间隔地跨越衬底以形成互连装置或结构的电互连电池。 互连设备在上表面上是完全可定制的或可编程的，以适应各种电气部件和与这些部件的连接。 电互连装置包括多个间歇间隔的第一对上，下信号线，与多个间歇间隔的第二对上，下信号线交织。 接合焊盘布置在相邻的上部和下部信号线对之间，并且可以与放置在表面层上的导电连接件连接。 每个焊盘包括一个或多个衬垫通孔，其垂直于上表面延伸到布置在较低层中的导电结构。 大约一半的焊盘阵列连接到电位导体。 上层信号线对不仅可以链接，而且可以被切割，以在目标位置之间形成更直接的路由。 此外，上下信号线被连接以使得迹线在整个互连结构上延伸以便易于测试。

    Process and laminate for the manufacture of through-hole plated electric printed-circuit boards
    80.
    发明授权
    Process and laminate for the manufacture of through-hole plated electric printed-circuit boards 失效
    用于制造通孔电镀印刷电路板的工艺和层压板

    公开(公告)号：US4770900A

    公开(公告)日：1988-09-13

    申请号：US27121

    申请日：1987-03-16

    Applicant: Markus Seibel

    Inventor： Markus Seibel

    IPC: H05K3/42 ,  H05K1/00 ,  H05K1/05 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  B05D5/12 ,  B44C1/22 ,  C03C25/06

    CPC classification number: H05K3/0094 ,  H05K1/0287 ,  H05K1/05 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394 ,  H05K3/062 ,  H05K3/108 ,  H05K3/426 ,  H05K3/427

    Abstract: A process for the manufacture of through-hole plated electric printed-circuit boards is described, in which a board of an insulating material is provided with plated-through holes which are arranged in a grid pattern and the walls of which are coated with a conductive metal layer. The board is covered with a conductive metal layer on at least one side thereof. After metallizing the holes, the metal layer is covered imagewise and the areas of the metal layer which are not covered are either reinforced by metal deposition or removed by etching. Together with the metal layer, part of the holes are covered in such a way that only the required portion of all holes act as conductive connections in the final product. The process of the present invention permits the large-scale manufacture of a predrilled or prepunched and premetallized base material for printed circuits.

    Abstract translation: 描述了一种用于制造通孔电镀印刷电路板的方法，其中绝缘材料的板设置有镀覆通孔，其布置成格栅图案，并且其壁被涂覆有导电 金属层。 该板在其至少一侧覆盖有导电金属层。 在金属化孔之后，金属层被成像地覆盖，未被覆盖的金属层的区域通过金属沉积或通过蚀刻去除。 与金属层一起，一部分孔被覆盖，使得只有所有孔的所需部分用作最终产品中的导电连接。 本发明的方法允许大规模制造用于印刷电路的预钻孔或预先预先金属化的基底材料。

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