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公开(公告)号：JP2001223116A
公开(公告)日：2001-08-17
申请号：JP2000377431
申请日：2000-12-12
Applicant: ST MICROELECTRONICS SA
Inventor： LEMAIRE FREDERIC
Abstract: PROBLEM TO BE SOLVED: To provide an inductance structure which is arranged on a semiconductor substrate, including an inductance and a conductive plane interposed between the semiconductor substrate and the inductance. SOLUTION: This inductance structure is equipped with the conductive plane including several separate conductive elements and several conductive tracks, wherein each conductive track connects at least the one conductive element to a contact point M of the conductive plane, and each of the conductive tracks is arranged so that the resultant of the electromotive forces induced therein by the inductances is substantially null.
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公开(公告)号：JP2001197494A
公开(公告)日：2001-07-19
申请号：JP2000335825
申请日：2000-11-02
Applicant: ST MICROELECTRONICS SA
Inventor： MARTY PIERRE
Abstract: PROBLEM TO BE SOLVED: To decode and display a main picture and a notice picture by using a single MPEG decoder and a memory. SOLUTION: In a circuit 12, a memory 6 is connected to a bus 8 to be accessed from a bidirectional bus 8, an MEPG decoder 4 is connected to the bus 8 to read encoding and decoding data of the memory and an encoded data output part is arranged, which is connected to the bus along a first path 16, by which reading is performed from the memory data of a first picture. A first picture display circuit 10 is connected to the bus to permit its input part to read data written by a decoder from the memory, a decimeter circuit 14 and a second picture display circuit 18 are included, the decimeter circuit is connected to a part between the output part of the decoder and the bus along a second path to write the second picture data displayed by reduction in the memory and, then, a second picture display circuit is connected to the bus to read data written by the decimeter circuit from the memory.
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公开(公告)号：JP2001196385A
公开(公告)日：2001-07-19
申请号：JP2000353964
申请日：2000-11-21
Applicant: ST MICROELECTRONICS SA
Inventor： MARTY MICHEL , DUTARTRE DIDIER , CHANTRE ALAIN , JOUAN SEBASTIEN , LLINARES PIERRE
IPC: H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/165 , H01L29/737
Abstract: PROBLEM TO BE SOLVED: To propose a vertical bipolar transistor which has a reduced low-frequency noise and allowable static parameters. SOLUTION: This vertical bipolar transistor includes an intrinsic collector 4 on an extrinsic collector layer 2 buried in a semiconductor substrate, a side separation area 5 surrounding the upper part of the intrinsic collector 4, an offset extrinsic collector well 60, a base 8 which is arranged on the intrinsic collector 4 and side separation area 5 and is composed of a semiconductor area including at least one silicon layer, and two doped emitters 11 surrounded with the base 8. The emitters 11 include a first part 110 which is made of single crystal and is directly in contact with the upper surface in the predetermined window 800, and a second part 111 formed of polycrystal. These two parts are isolated by an isolated oxide layer 112 arranged at an optional distance apart from an emitter base joint part.
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公开(公告)号：JP2001155492A
公开(公告)日：2001-06-08
申请号：JP2000299140
申请日：2000-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: PROBLEM TO BE SOLVED: To reduce occupied area of a shift register of an EEPROM integrated circuit serial access type memory. SOLUTION: This memory is provided with a data input DI, a data output D0, a memory plane MM constituted of memory words, a set LAT of a column register in which one register is combined with at least one memory word, a first means operated for loading directly binary data of a binary word received at a data input Di to each storage/switching latches HV0-HV7 of a column register R1 combined with memory words M0-M7 during writein operation of a binary word for the prescribed memory words M0-M7, and/or a second means operated for reading out continuously binary data stored in a memory cell of a memory word transmitting each read-out binary data to the data output D0 of a memory with a direct serial form during read-out operation of binary words in memory words.
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公开(公告)号：JP2001111460A
公开(公告)日：2001-04-20
申请号：JP2000259213
申请日：2000-08-29
Applicant: ST MICROELECTRONICS SA
Inventor： PRAT GILDAS , CHIANALE ALAIN
Abstract: PROBLEM TO BE SOLVED: To provide a new solution for suppressing echoes in a separation band transmission system. SOLUTION: A hybrid circuit forming an interface between a transmission line and a head for transmitting/receiving signals in frequency bands different by transmission and reception includes a line transformer and a means capable of separating a band coupled with an echo cancel means.
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Patent Agency Ranking
公开(公告)号：JP2001023999A
公开(公告)日：2001-01-26
申请号：JP2000183107
申请日：2000-06-19
Applicant: ST MICROELECTRONICS SA
Inventor： GRIS YVON
IPC: H01L29/73 , H01L21/331 , H01L29/165 , H01L29/732 , H01L29/737
Abstract: PROBLEM TO BE SOLVED: To form base-emitter junction by forming the base layer of a transistor in a common shape by selective epitaxy using a second conductivity type silicon layer, depositing first conductivity type heavily doped polysilicon, and by forming the emitter of the transistor. SOLUTION: In a region 8, one part of an epitaxial layer 3 is etched for forming a recessed part which partially extends below the inner periphery edge of spacers 11 and 12. A second conductivity type silicon layer is grown to thickness smaller than the depth of the recessed part, and the base layer of a transistor is formed in a common shape. Furthermore, a first polysilicon layer 19-1 is deposited on the recessed part at a high doping level, a thicker second polysilicon layer 19-2 is deposited at an ordinary doping level of heavy doping for composing a first conductivity type polisilicon layer, and a transistor emitter is formed.
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公开(公告)号：JP2000353091A
公开(公告)日：2000-12-19
申请号：JP2000134612
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , FEL BRUNO , DUCOUSSO LAURENT
Abstract: PROBLEM TO BE SOLVED: To provide a computer system in which both a superscaler mode and a VLIW mode are dealt with by instruction scheduling and data dependency between different instruction scan can be processed. SOLUTION: An instruction in a computer system is executed by plural parallel execution pipelines 13 to 16, checks 39 and 42 of dependency in the same row direction are supplied to the parallel pipelines 13 to 16, are executed between other instructions and, moreover, in response to the dependency in the same row direction to be detected, a control signal of a first or a second type is generated by depending upon whether or not the dependency can be released or not by activating a bypass or whether or not a temporary section is obtained for one of the pipelines.
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公开(公告)号：JP2000341884A
公开(公告)日：2000-12-08
申请号：JP2000104893
申请日：2000-04-06
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART LUC , BARDOUILLET MICHEL , ENGUENT JEAN-PIERRE
Abstract: PROBLEM TO BE SOLVED: To attain reduction in thermal effect related to remote power supply to a transponder through a readout/writing terminal, by detuning a transponder oscillating circuit when the transponder has a very close coupling relation to the readout/writing terminal. SOLUTION: This transponder 30 is constituted of a parallel oscillating circuit including an inductance L2 and a capacitor C2' between two terminals 11', 12' of the circuit. Between the terminals 11', 12', a capacitor C3 and a switch (for example, MOS transistor) K1 are serially connected. A switch K1 is controlled by a circuit 31 and is closed at the time of tuning operation. When it is in a closely coupled condition with the terminal, or respective antennas are positioned at a distance of less than 2 cm, for example, the oscillating circuit of the transponder is detuned (the switch K1 is off). It is thus possible to prevent heat generation of the transponder in radio-supplying operating power to the transponder approaching the terminal from the terminal.
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公开(公告)号：JP2000341883A
公开(公告)日：2000-12-08
申请号：JP2000083792
申请日：2000-03-24
Applicant: ST MICROELECTRONICS SA
Inventor： BARDOUILLET MICHEL
Abstract: PROBLEM TO BE SOLVED: To avoid generation of insufficient power supply and malfunction due to remarkable decrease in minimum supply voltage, by attaching a switched resistive means for changing transponder response to an oscillating circuit between a rectifying means and a one-way conduction means. SOLUTION: To transmit data from a transponder 10' to a readout/writing terminal station, a microcomputer 17 controls a modulating circuit of a resonance circuit (L2, C2). The modulating circuit is disposed on the upstream side of a capacitor Ca and including a resistive electronic switch (resistive switching means). The electronic switch connects a transistor T and a resistor R between a terminal 14 and a ground 15. A one-way conduction means 18 (diode DR) is serially connected between the first terminal 19 of the capacitor Ca and the terminal 14. The cathode of a diode DR is connected with the terminal 19 and its anode is connected with the terminal 14. It is thus possible to avoid generation of insufficient power supply and malfunction to a voltage regulator 16 and the microcomputer 17 due to remarkable decrease in minimum supply voltage.
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公开(公告)号：JP2000332647A
公开(公告)日：2000-11-30
申请号：JP2000104892
申请日：2000-04-06
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART LUC , BARDOUILLET MICHEL , ENGUENT JEAN-PIERRE
Abstract: PROBLEM TO BE SOLVED: To provide a method for duplex transmission between a terminal and a transponder in an electromagnetic transponder system. SOLUTION: Each of the terminal 40 and the transponder 10 is provided with an oscillation circuit 24, a modulation means and a demodulation means, the amplitude modulation transmission of a signal to be transmitted from the terminal 40 to the transponder 10 and the transmission of a signal from the transponder 10 to the terminal 40 and suited so as to follow the phase demodulation of the terminal 40 are simultaneously executed and an amplitude modulation rate is
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