公开(公告)号：KR1020050113793A

公开(公告)日：2005-12-05

申请号：KR1020040038901

申请日：2004-05-31

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  이웅 ,  임헌형 ,  이현덕 ,  나기수 ,  형용우 ,  이재동

IPC: H01L27/115

CPC classification number: H01L21/02323 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521

Abstract: A method of forming a dielectric layer having a reduced thickness according to embodiments of the invention includes forming a lower oxide layer on a substrate, and forming a nitride layer on the lower oxide layer. Then, a preliminary oxide layer is formed on the nitride layer. A radical oxidation process using oxygen radicals is performed on the preliminary oxide layer to form an upper oxide layer on the nitride layer. The dielectric layer includes an ONO composite layer consisting of the lower oxide layer, the nitride layer, and the upper oxide layer. Due to the decreased thickness of the dielectric layer, the dielectric layer has an improved capacitance and an increased coupling coefficient.

公开(公告)号：KR1020050028463A

公开(公告)日：2005-03-23

申请号：KR1020030064721

申请日：2003-09-18

Applicant: 삼성전자주식회사

Inventor： 이웅 ,  임헌형 ,  나기수 ,  유영섭 ,  이재동 ,  강만석 ,  남석우

IPC: H01L27/115

Abstract: A method for fabricating a non-volatile semiconductor device for improving cell threshold voltage uniformity and for preventing a control gate of a tungsten film from being oxidized is provided to improve scattering of a program threshold voltage by reinforcing a tunnel oxide layer at the edge of a gate stack pattern while avoiding the oxidation of the control gate. A gate stack pattern is formed on a silicon substrate, including a tunnel oxide layer, a floating gate, an insulation layer and a tungsten layer that are sequentially formed on the silicon substrate(200). The first nitride layer is formed on both sidewalls and the surface of the gate stack pattern and on the silicon substrate to prevent the control gate of the tungsten layer from being oxidized(220). An oxide layer is formed on the first nitride layer(240). The silicon substrate at the edge of the tunnel oxide layer is oxidized to reinforce the edge of the tunnel oxide layer(260). The second nitride layer is formed on the oxide layer(280). The first nitride layer, the oxide layer and the second nitride layer are etched to form a gate spacer on both sidewalls of the gate stack pattern(300).

Abstract translation: 提供了一种用于制造用于提高单元阈值电压均匀性和防止钨膜的控制栅极被氧化的非易失性半导体器件的方法，以通过加强在一边的边缘处的隧道氧化物层来改善程序阈值电压的散射 栅极堆叠图案，同时避免了控制栅极的氧化。 栅极堆叠图案形成在硅衬底上，其包括依次形成在硅衬底（200）上的隧道氧化物层，浮栅，绝缘层和钨层。 第一氮化物层形成在栅堆叠图案的两个侧壁和表面上以及硅衬底上，以防止钨层的控制栅极被氧化（220）。 在第一氮化物层（240）上形成氧化物层。 隧道氧化物层边缘的硅衬底被氧化以加强隧道氧化物层（260）的边缘。 第二氮化物层形成在氧化物层（280）上。 蚀刻第一氮化物层，氧化物层和第二氮化物层，以在栅堆叠图案（300）的两个侧壁上形成栅极间隔物。

公开(公告)号：KR100469128B1

公开(公告)日：2005-01-29

申请号：KR1020020068939

申请日：2002-11-07

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  임헌형 ,  이상훈

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/324 ,  H01L27/115 ,  H01L29/42324 ,  Y10S438/926

Abstract: Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530° C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580° C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.

Abstract translation: 本文公开了一种在具有自对准浅沟槽隔离（SA-STI）结构的非易失性存储器件中形成浮置栅极的方法。 首先，在具有SA-STI结构的半导体衬底上形成隧道氧化层。 接下来，在隧道氧化物层上以不低于约530℃的第一温度形成第一浮置栅极层。 然后在第一浮栅层上以不超过580℃的第二温度形成第二浮栅层。 在沉积第一浮置栅极层之后，原位沉积第二浮置栅极层以防止在第一浮置栅极层的表面上生长自然氧化物层。 因此，可以减少栅极电阻并缩短处理时间。

公开(公告)号：KR100466312B1

公开(公告)日：2005-01-13

申请号：KR1020020046612

申请日：2002-08-07

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  임헌형 ,  이상훈 ,  이우성

IPC: H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.

Abstract translation: 包括具有堆叠栅极侧壁和氧化物/氮化物/氧化物（ONO）层间电介质的堆叠栅极的半导体器件通过在包含氮的第一气氛中对堆叠栅极进行预退火来制造。 已经预退火的堆叠栅极的堆叠栅极侧壁的至少一部分被氧化。 然后在包括已被氧化的堆叠栅极侧壁的堆叠栅极上在包括氮的第二气氛中执行后退火。

公开(公告)号：KR1020040096377A

公开(公告)日：2004-11-16

申请号：KR1020030029446

申请日：2003-05-09

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  임헌형 ,  남석우 ,  김봉현 ,  이웅 ,  이상훈

IPC: H01L21/31

CPC classification number: H01L21/0223 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31662

Abstract: PURPOSE: A method for forming an oxide layer and an oxynitride layer is provided to remarkably improve the quality and uniformity of an oxide layer by oxidizing a substrate at a low pressure in a reaction furnace. CONSTITUTION: A substrate is loaded into a reaction furnace of the first pressure and the first temperature(S110). The temperature of the reaction furnace ramps up to the second temperature at the second pressure while reaction gas is inserted to firstly oxidize the substrate(S120). The first pressure is 0.03-3 torr and the first temperature is 300-550 deg.C. The second pressure is 0.3-20 torr and the second temperature is 550-950 deg.C.

Abstract translation: 目的：提供一种形成氧化物层和氧氮化物层的方法，通过在反应炉中低压氧化基板，显着提高氧化物层的质量和均匀性。 构成：将基板装载到第一压力和第一温度的反应炉中（S110）。 反应炉的温度在第二压力下升至第二温度，同时插入反应气体以首先氧化基板（S120）。 第一压力为0.03-3乇，第一温度为300-550℃。 第二压力为0.3-20乇，第二温度为550-950℃。

公开(公告)号：KR1020040050241A

公开(公告)日：2004-06-16

申请号：KR1020020078013

申请日：2002-12-09

Applicant: 삼성전자주식회사

Inventor： 신승목 ,  임헌형 ,  이공수 ,  이상훈

IPC: H01L21/8247

Abstract: PURPOSE: A method for fabricating a non-volatile memory cell is provided to prevent the loss of data and the leakage current by blocking the diffusion of mobile charges to a gate spacer. CONSTITUTION: A gate electrode is formed on a surface of a semiconductor substrate(100). A gate spacer is formed on a lateral face of the gate electrode. A source/drain region(150) is formed by implanting the first impurities into the surface of the exposed semiconductor substrate by using the gate electrode having the gate spacer as an ion implantation mask. The ions of the source/drain region are activated. Chloride ions for capturing mobile electrons are diffused within the gate spacer. An interlayer dielectric(160) is formed by filling up an insulating material into the resultant.

Abstract translation: 目的：提供一种用于制造非易失性存储单元的方法，以通过阻止移动电荷向栅极间隔物的扩散来防止数据损失和漏电流。 构成：在半导体衬底（100）的表面上形成栅电极。 栅极间隔物形成在栅电极的侧面上。 通过使用具有栅极间隔物的栅电极作为离子注入掩模，将第一杂质注入暴露的半导体衬底的表面中来形成源/漏区（150）。 源极/漏极区域的离子被激活。 用于捕获移动电子的氯离子在栅极间隔物内扩散。 通过向所得物填充绝缘材料形成层间电介质（160）。

公开(公告)号：KR1020040000972A

公开(公告)日：2004-01-07

申请号：KR1020020036014

申请日：2002-06-26

Applicant: 삼성전자주식회사

Inventor： 이우성 ,  임헌형 ,  강만석

IPC: H01L27/115

Abstract: PURPOSE: A method of manufacturing non-volatile memory device is provided to improve morphology of floating gate pattern. CONSTITUTION: After a gate oxide layer(104) is grown on a semiconductor substrate(100), the first conductive layer for a floating gate is deposited upon the gate oxide layer. A buffer oxide layer is formed on the first conductive layer and a reflection stop layer is formed on the buffer layer. The reflection stop layer is then patterned to form a reflection stop pattern. A spacer(114a) is formed at the side wall of the reflection stop pattern. By using the spacer(114a) as an etch-stop, the buffer layer and the first conductive layer are etched to form the first conductive layer pattern(106a) and the buffer layer pattern(108a). After an oxide layer(116) is formed at the side wall of the first conductive layer pattern(106a), the spacer(114a), the oxide layer(116) and the buffer layer pattern(108a) are removed.

Abstract translation: 目的：提供一种制造非易失性存储器件的方法，以改善浮栅图案的形态。 构成：在半导体衬底（100）上生长栅极氧化层（104）之后，浮栅的第一导电层沉积在栅氧化层上。 在第一导电层上形成缓冲氧化物层，在缓冲层上形成反射阻挡层。 然后将反射停止层图案化以形成反射停止图案。 在反射停止图案的侧壁形成间隔物（114a）。 通过使用间隔物（114a）作为蚀刻停止层，对缓冲层和第一导电层进行蚀刻以形成第一导电层图案（106a）和缓冲层图案（108a）。 在第一导电层图案（106a）的侧壁上形成氧化物层（116）之后，去除间隔物（114a），氧化物层（116）和缓冲层图案（108a）。

公开(公告)号：KR1020030088750A

公开(公告)日：2003-11-20

申请号：KR1020020026616

申请日：2002-05-15

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  박영욱 ,  임헌형 ,  허형조

IPC: H01L21/31

Abstract: PURPOSE: A method for manufacturing a high integrated device is provided to be capable of forming a nitride layer having good step coverage at low temperature by using ALD(Atomic Layer Deposition). CONSTITUTION: A semiconductor substrate(100) is defined to a field region and an active region. A transistor(153) is formed on the substrate. A cobalt silicide layer(180a,180a') is selectively formed on the substrate and the transistor. A nitride layer(190) is formed on the entire surface of the resultant structure by ALD. An insulating layer(190a) is deposited on the nitride layer(190). A contact hole(196) is formed to expose the cobalt silicide layer and the field region by sequentially etching the insulating layer and the nitride layer. A metal contact film(197) is filled into the contact hole.

Abstract translation: 目的：提供一种制造高集成器件的方法，以便能够通过使用ALD（原子层沉积）在低温下形成具有良好阶梯覆盖的氮化物层。 构成：将半导体衬底（100）定义为场区域和有源区域。 晶体管（153）形成在衬底上。 选择性地在衬底和晶体管上形成硅化钴层（180a，180a'）。 通过ALD在所得结构的整个表面上形成氮化物层（190）。 绝缘层（190a）沉积在氮化物层（190）上。 通过依次蚀刻绝缘层和氮化物层，形成接触孔（196）以露出硅化钴层和场区。 金属接触膜（197）被填充到接触孔中。

公开(公告)号：KR1020030065702A

公开(公告)日：2003-08-09

申请号：KR1020020005423

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 임헌형 ,  형용우 ,  허형조 ,  유영섭

IPC: H01L29/788

Abstract: PURPOSE: A method for fabricating a floating gate type non-volatile memory device is provided to increase the capacitance between a floating gate electrode and a control gate electrode and enhance a coupling ratio by forming an insulating layer having a high dielectric constant between the floating gate electrode and the control gate electrode. CONSTITUTION: An isolation layer(6) is formed on a predetermined region of a semiconductor substrate(1) in order to define an active region. A tunnel oxide layer(2) and a floating gate line are sequentially stacked on an upper portion of the active region. A dielectric layer(9) including an insulating layer is formed on the entire surface of the semiconductor substrate including the floating gate line. A dielectric constant of the insulating layer is higher than the dielectric constant of a silicon nitride layer. A conductive layer of control gate is formed on the dielectric layer. A floating gate electrode(8a), the dielectric layer, and a control gate electrode(12) are formed by patterning sequentially the conductive layer of control gate, the dielectric layer, and the floating gate line.

Abstract translation: 目的：提供一种用于制造浮动栅型非易失性存储器件的方法，以增加浮栅和控制栅电极之间的电容，并通过在浮置栅极之间形成具有高介电常数的绝缘层来提高耦合比 电极和控制栅电极。 构成：为了限定有源区，在半导体衬底（1）的预定区域上形成隔离层（6）。 隧道氧化物层（2）和浮栅线依次层叠在有源区的上部。 在包括浮动栅极线的半导体衬底的整个表面上形成包括绝缘层的电介质层（9）。 绝缘层的介电常数高于氮化硅层的介电常数。 在电介质层上形成控制栅的导电层。 通过对控制栅极，电介质层和浮置栅极线的导电层顺序构图，形成浮栅电极（8a），电介质层和控制栅电极（12）。

公开(公告)号：KR1020010003954A

公开(公告)日：2001-01-15

申请号：KR1019990024508

申请日：1999-06-26

Applicant: 삼성전자주식회사

Inventor： 임헌형 ,  안병호

IPC: H01L27/10

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to simplify a manufacturing process and to embody a storage electrode layer having a large surface area, by forming hemispherical crystal grains on a lightly doped amorphous silicon layer. CONSTITUTION: Hemispherical crystal grains(130) are grown on an amorphous silicon layer to form a bent polycrystalline silicon layer(126a). The first gas for impurity doping is injected into the polycrystalline silicon layer to improve conductivity of the bent polycrystalline silicon layer. The second gas is injected by an in-situ process to form a high dielectric layer(134) on the polycrystalline silicon layer doped with the impurities.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以通过在轻掺杂的非晶硅层上形成半球形晶粒来简化制造工艺并体现具有大表面积的存储电极层。 构成：半球形晶粒（130）生长在非晶硅层上以形成弯曲的多晶硅层（126a）。 将第一种用于杂质掺杂的气体注入到多晶硅层中以改善弯曲多晶硅层的导电性。 通过原位工艺注入第二气体，以在掺杂有杂质的多晶硅层上形成高介电层（134）。