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    메모리 장치, 메모리 컨트롤러, 메모리 시스템 및 이의 동작 방법
    81.
    发明公开
    메모리 장치, 메모리 컨트롤러, 메모리 시스템 및 이의 동작 방법 审中-实审
    存储器件，存储器控制器，存储器系统及其操作方法

    公开(公告)号：KR1020130119545A

    公开(公告)日：2013-11-01

    申请号：KR1020120042413

    申请日：2012-04-24

    Applicant: 삼성전자주식회사

    Inventor： 서은성 ,  박철우 ,  황홍선

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C7/00 ,  G11C11/40611

    Abstract: A memory system includes at least one memory device and a memory controller. The memory device includes a refresh request circuit which generates a refresh data signal which includes a refresh request signal according to each data retention time of a plurality of memory cells. The memory controller controls the memory device by scheduling an operation command about the operation of the memory device by including the refresh request signal.

    Abstract translation: 存储器系统包括至少一个存储器设备和存储器控制器。 存储装置包括根据多个存储单元的每个数据保留时间产生包括刷新请求信号的刷新数据信号的刷新请求电路。 存储器控制器通过包括刷新请求信号调度关于存储器件的操作的操作命令来控制存储器件。

    메모리 특성 정보를 저장하는 반도체 메모리 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 반도체 메모리 장치의 동작방법
    82.
    发明公开
    메모리 특성 정보를 저장하는 반도체 메모리 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 반도체 메모리 장치의 동작방법 无效
    半导体存储器件存储器存储器特征信息，存储器模块和存储器系统及其操作方法

    公开(公告)号：KR1020130078455A

    公开(公告)日：2013-07-10

    申请号：KR1020110147415

    申请日：2011-12-30

    Applicant: 삼성전자주식회사

    Inventor： 유학수 ,  최주선 ,  황홍선

    IPC: G11C11/4063 ,  G11C11/408 ,  G11C7/10

    CPC classification number: G11C11/4063 ,  G11C11/406 ,  G11C14/00 ,  G11C14/0018 ,  G11C16/06 ,  G11C29/783 ,  G11C2211/4061

    Abstract: PURPOSE: A semiconductor memory device storing memory characteristic information, a memory module including the same, a memory system, and an operation method of the semiconductor memory device are provided to reduce the impact of a weak cell or a weak page on a memory operation by managing the memory operation using the stored characteristic information. CONSTITUTION: A cell array includes multiple regions accessed by a first address. A non-volatile array (1110) stores group information in which each region is included for the multiple regions classified into two groups according to memory characteristics. The group information is successively stored in the non-volatile array according to a first address value of the regions.

    Abstract translation: 目的：提供一种存储存储特性信息的半导体存储器件，包括该半导体存储器件的存储器模块，存储器系统和操作方法，以减少弱电池或弱电压对存储器操作的影响 使用存储的特征信息来管理存储器操作。 构成：单元阵列包括由第一个地址访问的多个区域。 根据存储特性，非易失性阵列（1110）存储组信息，其中包括分为两组的多个区域的每个区域。 组信息根据区域的第一地址值被连续地存储在非易失性阵列中。

    데이터 리드회로, 이를 포함하는 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 데이터 리드 방법
    83.
    发明公开
    데이터 리드회로, 이를 포함하는 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 데이터 리드 방법 无效
    数据读取电路，具有该读取电路的非易失性存储器件和用于读取非易失性存储器件的数据的方法

    公开(公告)号：KR1020130022540A

    公开(公告)日：2013-03-07

    申请号：KR1020110085146

    申请日：2011-08-25

    Applicant: 삼성전자주식회사

    Inventor： 김찬경 ,  황홍선 ,  박철우 ,  강상범 ,  오형록

    IPC: G11C16/26 ,  G11C16/32

    CPC classification number: G11C16/26 ,  G11C11/1673 ,  G11C11/1697 ,  G11C11/2273 ,  G11C11/2297 ,  G11C13/0038 ,  G11C13/004 ,  G11C16/30

    Abstract: PURPOSE: A data read circuit, a nonvolatile memory device including the same, and a method for reading data in the nonvolatile memory device are provided to improve the reliability of read data by using a plurality of reference voltages. CONSTITUTION: A cell array includes nonvolatile memory cells. A bit line is connected to the nonvolatile memory cell and transmits a data voltage(VSA). A sense amplifier circuit(1151) receives a data voltage through a first input unit and receives two reference voltages(VREFH,VREFL) through a second input unit. The sense amplifier circuit generates read data by differentially amplifying input signals inputted to the first and second input units in a data read operation.

    Abstract translation: 目的：提供数据读取电路，包括该数据读取电路的非易失性存储器件以及用于读取非易失性存储器件中的数据的方法，以通过使用多个参考电压来提高读取数据的可靠性。 构成：单元阵列包括非易失性存储单元。 位线连接到非易失性存储单元并发送数据电压（VSA）。 读出放大器电路（1151）通过第一输入单元接收数据电压，并通过第二输入单元接收两个参考电压（VREFH，VREFL）。 读出放大器电路通过在数据读取操作中差分放大输入到第一和第二输入单元的输入信号来产生读取数据。

    수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
    84.
    发明公开
    수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법 无效
    包括垂直通道晶体管的半导体器件及其制造方法

    公开(公告)号：KR1020130020333A

    公开(公告)日：2013-02-27

    申请号：KR1020110082910

    申请日：2011-08-19

    Applicant: 삼성전자주식회사

    Inventor： 유학수 ,  박철우 ,  정현우 ,  황홍선 ,  김수아 ,  최현호

    IPC: H01L29/78 ,  H01L21/768 ,  H01L21/336

    CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66712

    Abstract: PURPOSE: A semiconductor device including a vertical channel transistor and a manufacturing method thereof are provided to prevent a channel region from being floated by connecting channel regions of active pillars to a string body connection unit. CONSTITUTION: A plurality of active pillars(AP) include a top dopant region, a bottom dopant region, and a channel region(C). The channel region is arranged between the top dopant region and the bottom dopant region. A contact gate electrode(CG) is contacted with a word line extended in a first direction and is extended near the channel region. A bit line is extended in a second direction across the first direction and is contacted with the bottom dopant region. A string body connection unit(SB) connects the channel regions of adjacent active pillars.

    Abstract translation: 目的：提供一种包括垂直沟道晶体管及其制造方法的半导体器件，以通过将活性柱的沟道区域连接到串体连接单元来防止沟道区域浮起。 构成：多个活性柱（AP）包括顶部掺杂区域，底部掺杂剂区域和沟道区域（C）。 沟道区布置在顶部掺杂区域和底部掺杂区域之间。 接触栅电极（CG）与在第一方向上延伸的字线接触并在沟道区附近延伸。 位线沿着第一方向在第二方向上延伸并与底部掺杂剂区域接触。 弦体连接单元（SB）连接相邻活动柱的通道区域。

    히든 타이밍 파라미터들을 관리하는 메모리 장치
    85.
    发明公开
    히든 타이밍 파라미터들을 관리하는 메모리 장치 有权
    用于实施隐藏时间参数管理的存储器件

    公开(公告)号：KR1020130018487A

    公开(公告)日：2013-02-25

    申请号：KR1020120037553

    申请日：2012-04-10

    Applicant: 삼성전자주식회사

    Inventor： 강욱성 ,  박철우 ,  유학수 ,  황홍선

    IPC: G11C7/22 ,  G11C8/18 ,  G11C7/12 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

    Abstract: PURPOSE: A memory device for managing hidden timing parameters is provided to secure timing parameter margin by hiding the timing parameters from a memory controller. CONSTITUTION: A memory device includes a plurality of banks in which a plurality of memory cells are arranged. Each bank includes two or more sub banks. In a sub bank interleave method to continuously operate the sub banks in one bank one by one, a continuous operation between sub banks is set at low active-to-low active time interval between different banks.

    Abstract translation: 目的：提供一种用于管理隐藏定时参数的存储器件，以通过从存储器控制器隐藏定时参数来保护定时参数余量。 构成：存储器件包括多个存储单元，多个存储单元布置在该存储单元中。 每个银行都有两个或更多的子银行。 在子库交织方法中，一个接一个地连续操作一个子组中的子组，子组之间的连续操作被设置为不同组之间的低有效 - 低活动时间间隔。

    다이나믹 램 장치의 플레이트 전압 발생 회로
    89.
    发明授权
    다이나믹 램 장치의 플레이트 전압 발생 회로 失效

    公开(公告)号：KR100449270B1

    公开(公告)日：2004-12-17

    申请号：KR1019970036643

    申请日：1997-07-31

    Applicant: 삼성전자주식회사

    Inventor： 이창호 ,  황홍선

    IPC: G11C5/14

    Abstract: PURPOSE: A plate voltage generation circuit of a DRAM(Dynamic RAM) device is provided to generate different plate voltages respectively during a normal read/write operation and a burn-in test operation in a package state. CONSTITUTION: According to the DRAM device, a plate voltage generating circuit(400) generates a plate voltage(Vp) in response to an internal power supply voltage during a normal read/write operation. A unit generates the first plate voltage with one of the first level voltage and the second level voltage according to data stored in a cell capacitor during a burn-in test operation. A level detection circuit(200) generates the first detection signal(PDET) by detecting whether an external power supply voltage is lower or higher than a reference voltage(VREF). A burn-in mode detecting circuit(210) generates a pair of second detection signals indicating the burn-in test operation. A unit disables the plate voltage generating circuit during the normal read/write operation if the second detection signals indicate the burn-in test operation. And a unit enables the plate voltage generating circuit during the burn-in test operation if the second detection signals indicate the burn-in test operation.

    오픈 드레인 방식의 출력단을 구동하는 출력 드라이버
    90.
    发明公开
    오픈 드레인 방식의 출력단을 구동하는 출력 드라이버 失效
    驱动开放式输出端子类型的输出驱动器

    公开(公告)号：KR1020010073707A

    公开(公告)日：2001-08-01

    申请号：KR1020000002487

    申请日：2000-01-19

    Applicant: 삼성전자주식회사

    Inventor： 문병모 ,  문병식 ,  황홍선

    IPC: G11C7/04

    Abstract: PURPOSE: An output driver of driving an open drain type of output terminal is provided to realize a stable driving capability though the properties of transistors is degraded by PVT variation. CONSTITUTION: In an output driver(100) of driving an open drain type of an output terminal, the first and second data input parts(12,22) receive data responding to a clock signal and a delay clock signal. The first and second free drivers(14,24) are driven respectively depending on the outputs of the first and second data input parts. The first sub-driver(18) performs a pull-swing of the output level of the first free-driver responding to the first to third control signals and the output of the first data input part. The second sub-driver(28) performs a pull-swing of the output level of the second free-driver responding to the first to third control signals and the output of the second data input part. The first pull-down(16) transistor having an open drain type is connected to an output pad. The first pull-down transistor is controlled by the outputs of the first free-driver and the first sub-driver. The second pull-down transistor(26) having an open drain type is connected to the output pad. The second pull-down transistor is controlled by the outputs of the second free-driver and the second sub-driver.

    Abstract translation: 目的：提供驱动开漏型输出端子的输出驱动器，以实现稳定的驱动能力，尽管晶体管的性能由于PVT变化而降低。 构成：在驱动开漏型输出端子的输出驱动器（100）中，第一和第二数据输入部件（12,22）接收响应时钟信号和延迟时钟信号的数据。 第一和第二自由驱动器（14,24）分别根据第一和第二数据输入部分的输出驱动。 第一子驱动器（18）响应于第一至第三控制信号和第一数据输入部分的输出，执行第一自由驱动器的输出电平的拉动。 第二子驱动器（28）响应于第一至第三控制信号和第二数据输入部分的输出执行第二自由驱动器的输出电平的拉动。 具有开漏型的第一下拉（16）晶体管连接到输出焊盘。 第一下拉晶体管由第一自由驱动器和第一副驱动器的输出控制。 具有开漏型的第二下拉晶体管（26）连接到输出焊盘。 第二下拉晶体管由第二自由驱动器和第二副驱动器的输出控制。

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