公开(公告)号：DE69625038T2

公开(公告)日：2003-07-10

申请号：DE69625038

申请日：1996-09-06

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

Abstract: The DRAM comprises an array of memory cells in rows and columns. A word line is provided in each row and a bit line is provided in each column. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

公开(公告)号：DE69906406D1

公开(公告)日：2003-05-08

申请号：DE69906406

申请日：1999-01-29

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  PFEFFERL KARL-PETER

IPC: G11C29/04 ,  G11C29/00 ,  G06F11/20

Abstract: A method and apparatus for repairing a memory device through a selective domain redundancy replacement (SDRR) arrangement, following the manufacture and test of the memory device. A redundancy array supporting the primary arrays forming the memory includes a plurality of redundancy groups, at least one of which contains two redundancy units. A redundancy replacement is hierarchically realized by a domain that includes a faulty element within the redundancy group, and by a redundancy unit that repairs the fault within the selected domain. SDRR allows a domain to customize the optimum number and size redundancy units according to existing fault distributions, while achieving a substantially saving in real estate, particularly over the conventional flexible redundancy replacement, in term of the number of fuses (10-20%). By combining several types of redundancy groups, each having a different number of redundancy elements, full flexible redundancy replacement can also be achieved. Consequently, this approach compensates for the drawback of existing intra-block replacements, flexible redundancy replacements, and variable domain redundancy replacements, while improving repairability irrespective of the fault distribution within the memory device.

公开(公告)号：DE69618857T2

公开(公告)日：2002-09-12

申请号：DE69618857

申请日：1996-05-31

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C29/12 ,  G11C29/06 ,  G11C29/10 ,  G11C29/00

Abstract: A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

公开(公告)号：DE69614905T2

公开(公告)日：2002-04-04

申请号：DE69614905

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

Abstract: The memory comprises several word-lines and complementary bit-line pairs. A source of precharge voltage for precharges the complementary bit-line pairs. Several precharge equalisation circuits each of which comprises three field effect transistors. The one FET is connected across a corresponding complementary pair of bit-lines and the other two FET's are connected in series with a respective complementary pair of bit-lines. The gates of each of the FET's are connected to receive a precharge equalisation control signal. The precharge equalisation circuits is connected to the source of the precharge voltage. One precharge equalisation circuit precharges each of the complementary bit-line pairs. A current limiter limits the precharge current flowing into the complementary bit-line pairs to a precharge current limit value. The current limiter comprises a FET which is biased to limit current flow through the transistors to the precharge current limit value.

公开(公告)号：DE69618857D1

公开(公告)日：2002-03-14

申请号：DE69618857

申请日：1996-05-31

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C29/12 ,  G11C29/06 ,  G11C29/10 ,  G11C29/00

Abstract: A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

公开(公告)号：SG53118A1

公开(公告)日：1998-09-28

申请号：SG1997003935

申请日：1997-11-01

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

Abstract: Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

公开(公告)号：GB2509823B

公开(公告)日：2015-11-11

申请号：GB201320411

申请日：2013-11-19

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN ,  ROSENBLATT SAMI

IPC: G06F21/44 ,  G06F21/30

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

公开(公告)号：IN2203CHN2014A

公开(公告)日：2015-06-12

申请号：IN2203CHN2014

申请日：2014-03-21

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROBSON NORMAN W ,  ROSENBLATT SAMI

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails adjusted by a BIST engine 625 wherein the fail numbers 803 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation resulting in a more secure identification.

公开(公告)号：MY134640A

公开(公告)日：2007-12-31

申请号：MYPI0304823

申请日：1998-02-26

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C7/00 ,  G11C29/04 ,  G11C29/00

Abstract: A VARIABLE SIZE REDUNDANCY REPLACEMENT (VSRR) ARRANGEMENT FOR MAKING A MEMORY FAULT-TOLERANT. A REDUNDANCY ARRAY SUPPORTING THE MEMORY INCLUDES A PLURALITY OF VARIABLE SIZE REDUNDANCY UNITS, EACH OF WHICH ENCOMPASSES A PLURALITY OF REDUNDANCY ELEMENTS. THE REDUNDANCY UNITS, USED FOR REPAIRING FAULTS IN THE MEMORY, ARE INDEPENDENTLY CONTROLLED. ALL THE REDUNDANCY ELEMENTS WITHIN A REPAIR UNIT ARE PREFERABLY REPLACED SIMULTANEOUSLY. THE REDUNDANCY ELEMENTS IN THE REDUNDANCY UNIT ARE CONTROLLED BY DECODING ADDRESS LINES. THE VARIABLE SIZE THAT CHARACTERIZES THIS CONFIGURATION MAKES IT POSSIBLE TO CHOOSE THE MOST EFFECTIVE REDUNDANCY UNIT, AND IN PARTICULAR, THE ONE MOST CLOSELY FITTING THE SIZE OF THE CLUSTER OF FAILURES TO BE REPLACED. THIS CONFIGURATION SIGNIFICANTLY REDUCES THE OVERHEAD CREATED BY ADDED REDUNDANCY ELEMENTS AND CONTROL CIRCUITRY, WHILE IMPROVING THE ACCESS SPEED AND REDUCING POWER CONSUMPTION. FINALLY, A FAULT-TOLERANT BLOCK REDUNDANCY CONTROLLED BY A PRIORITY DECODER MAKES IT POSSIBLE TO USE VSRR UNITS FOR REPAIRING FAULTS IN THE BLOCK REDUNDANCY PRIOR TO ITS USE FOR REPLACING A DEFECTIVE BLOCK WITHIN THE MEMORY.(FIG. 2)

公开(公告)号：DE60035630D1

公开(公告)日：2007-09-06

申请号：DE60035630

申请日：2000-01-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.