公开(公告)号：DE10215666A1

公开(公告)日：2002-11-07

申请号：DE10215666

申请日：2002-04-09

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS ,  MALIK RAIEEV ,  DIVAKARUNI RAMA ,  MANDELMAN JACK A ,  JAIPRAKASH V C

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242

Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

公开(公告)号：HK1035260A1

公开(公告)日：2001-11-16

申请号：HK01105921

申请日：2001-08-22

Applicant: IBM ,  SIEMENS CORP

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L20060101 ,  H01L

公开(公告)号：DE69934357D1

公开(公告)日：2007-01-25

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

公开(公告)号：AU2002368388A1

公开(公告)日：2004-06-18

申请号：AU2002368388

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

公开(公告)号：DE69904690T2

公开(公告)日：2003-09-18

申请号：DE69904690

申请日：1999-10-14

Applicant: SIEMENS AG ,  IBM

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells (301) of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells (300) of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators (302) adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots (320) in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

公开(公告)号：DE10220542A1

公开(公告)日：2002-12-05

申请号：DE10220542

申请日：2002-05-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL J ,  MANDELMAN JACK A ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.

公开(公告)号：SG64968A1

公开(公告)日：1999-05-25

申请号：SG1997000351

申请日：1997-02-17

Applicant: SIEMENS AG ,  IBM

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10 ,  H01L21/82 ,  H01L21/70

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：DE10361272B4

公开(公告)日：2012-01-05

申请号：DE10361272

申请日：2003-12-24

Applicant: QIMONDA AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242 ,  H01L27/108

Abstract: Verfahren zum Ausbilden einer DRAM-Speicherzelle (100), umfassend: Ausbilden eines Grabens mit einer Grabenwandung in einem Halbleitersubstrat (10); Ausbilden eines Grabenkondensators (20) in einem unteren Bereich des Grabens mit einer dielektrischen Kondensatorschicht auf einer Innenfläche des Grabens, mit einem isolierenden Grabenkragen (110) in einem oberen Bereich des Grabenkondensators (20) und einer mittleren Kondensatorelektrode (105); Zurücksetzen der mittleren Kondensatorelektrode (105) auf eine Kondensatortiefe, wobei eine Elektrodenoberfläche verbleibt; Zurücksetzen des isolierenden Grabenkragens (110) auf eine Ebene unterhalb der Elektrodenoberfläche, wobei eine Buried-Strap-Öffnung (113) zwischen der mittleren Kondensatorelektrode (105) und der Grabenwandung ausgebildet und die Buried-Strap-Öffnung (113) mit einer ersten provisorischen Isolierschicht (112) aufgefüllt wird; Ausbilden einer Anzahl von Isolationsgräben in dem Halbleitersubstrat (10) mit einer bestimmten Isolationsgrabentiefe und Auffüllen der Isolationsgräben mit einem isolierenden Material (15); Ausbilden eines leitenden Buried-Strap (114), der mit der mittleren Kondensatorelektrode (105) in Kontakt steht und an die Grabenwandung angrenzt, wobei die...

公开(公告)号：DE60223419T2

公开(公告)日：2008-09-04

申请号：DE60223419

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

公开(公告)号：MY126185A

公开(公告)日：2006-09-29

申请号：MYPI20023100

申请日：2002-08-22

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK A

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/94 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L31/113

Abstract: A WRAPPED-GATE TRANSISTOR INCLUDES A SUBSTRATE HAVING AN UPPER SURFACE AND FIRST AND SECOND SIDE SURFACES OPPOSING TO EACH OTHER.SOURCE AND DRAIN REGIONS (28) ARE FORMED IN THE SUBSTRATE WITH A CHANNEL REGION THEREBETWEEN. THE CHANNEL REGION EXTENDS FROM THE FIRST SIDE SURFACE TO THE SECOND SIDE SURFACES OF THE SUBSTRATE. A GATE DIELECTRIC LAYER (40) IS FORMED ON THE SUBSTRATE. A GATE ELECTRODE (42) IS FORMED ON THE GATE DIELECTRIC LAYER TO COVER THE CHANNEL REGION FROM THE UPPER SURFACE AND THE FIRST AND SECOND SIDE SURFACES WITH THE GATE DIELECTRIC THEREBETWEEN. THE SUBSTRATE IS A SILICON ISLAND FORMED ON AN INSULATION LAYER OF AN SOI (SILICON-ON-INSULATOR) SUBSTRATE OR ON A CONVENTIONAL NON-SOI SUBSTRATE, AND HAS FOUR SIDE SURFACES INCLUDING THE FIRST AND SECOND SIDE SURFACES. THE SOURCE AND DRAIN REGIONS ARE FORMED ON THE PORTIONS OF THE SUBSTRATE ADJOINING THE THIRD AND FOURTH SIDE SURFACES WHICH ARE PERPENDICULAR TO THE FIRST AND SECOND SIDE SURFACES. THE WRAPPEDGATE STRUCTURE PROVIDES A BETTER AND QUICKER POTENTIAL CONTROL WITHIN THE CHANNEL AREA, WHICH YIELDS STEEP SUB-THRESHOLD SLOPE AND LOW SENSITIVITY TO THE "BODY-TO-SOURCE" VOLTAGE.(FIG 18A)