公开(公告)号：US20240162191A1

公开(公告)日：2024-05-16

申请号：US18054211

申请日：2022-11-10

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Changhua Liu ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Mohammad Mamunur Rahman

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/0655 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.

公开(公告)号：US20240113075A1

公开(公告)日：2024-04-04

申请号：US17956363

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：US20240113006A1

公开(公告)日：2024-04-04

申请号：US17937519

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

公开(公告)号：US11948848B2

公开(公告)日：2024-04-02

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Oscar Ojeda ,  Leonel Arana ,  Suddhasattwa Nad ,  Robert May ,  Hiroki Tanaka ,  Brandon C. Marin

IPC: H01L23/31 ,  H01L21/283 ,  H01L23/498 ,  H05K1/02 ,  H05K3/06

CPC classification number: H01L23/3114 ,  H01L21/283 ,  H05K1/0296 ,  H05K3/061

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20240079337A1

公开(公告)日：2024-03-07

申请号：US17929471

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tchefor Ndukum ,  Kristof Kuwawi Darmawikarta ,  Sheng Li ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

公开(公告)号：US11855125B2

公开(公告)日：2023-12-26

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Brandon C. Marin ,  Jeremy Ecton ,  Hiroki Tanaka ,  Frank Truong

IPC: H01L21/48 ,  H01G4/008 ,  H01G4/28 ,  H01G4/12 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/28 ,  H01L21/4846

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US11694898B2

公开(公告)日：2023-07-04

申请号：US16363688

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy Ecton ,  Bai Nie ,  Rahul Manepalli ,  Marcel Wall

IPC: G09G3/20 ,  H01L21/28 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/2815 ,  H01L21/4853 ,  H01L24/17 ,  H01L2224/17051

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

公开(公告)号：US20230080454A1

公开(公告)日：2023-03-16

申请号：US17473694

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Brandon C. Marin ,  Debendra Mallik ,  Tarek A. Ibrahim ,  Jeremy Ecton ,  Omkar G. Karhade ,  Bharat Prasad Penmecha ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Mitul Modi ,  Bai Nie

IPC: G02B6/12 ,  H01L23/48

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：US20220199427A1

公开(公告)日：2022-06-23

申请号：US17132282

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Oladeji Fadayomi ,  Jeremy Ecton ,  Oscar Ojeda

IPC: H01L21/48 ,  H01L23/498

Abstract: An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.

公开(公告)号：US20210375746A1

公开(公告)日：2021-12-02

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.