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    Barrier layer and fabricating method of the same
    83.
    发明专利
    Barrier layer and fabricating method of the same 未知

    公开(公告)号：GB2341484B

    公开(公告)日：2000-12-06

    申请号：GB9819997

    申请日：1998-09-14

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI ,  HUANG YIMIN

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/532

    Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

    Self-aligned borderless contacts and local interconnections manufacture
    85.
    发明专利
    Self-aligned borderless contacts and local interconnections manufacture 未知

    公开(公告)号：NL1008773C2

    公开(公告)日：1999-10-04

    申请号：NL1008773

    申请日：1998-04-01

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/768

    Abstract: The integral process is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. The method comprises (i) providing a substrate having shallow trench isolation areas (31) for defining at least a local interconnection and an active area, (ii) forming first and second gate electrodes respectively on the local interconnect area and the active area, each electrode respectively having a gate oxide layer (32), a polysilicon layer (33a,b) above the gate oxide layer, a silicide layer (34a,b) and a first isolation layer (35a,b), (iii) forming source/drain regions (36) in the substrate by ion implantation using the gate electrodes as masks, (iv) forming spacers (37a,b,c,d) around the gate electrodes, (v) etching a portion of the first gate electrode and a portion of the first spacer to expose a portion of the silicide layer of the first gate electrode, (vi) eliminating the exposed portion of the gate oxide layer, (vii) forming a self-aligned silicide layer (42a,b,c) on the surface of the source/drain regions, and (viii) forming a second isolation layer (44) and a dielectric layer (43a) over the second isolation layer, etching a portion of the second isolation layer and the dielectric layer to form a first opening above the local interconnect area and a second opening above the active area. The first opening exposes portions of the first gate electrode, the silicide layer, the first spacer and the self-aligned silicide layer on the surface of the source/drain region of the first electrode. The second opening exposes portions of the second gate electrode, the second spacer and the self-aligned silicide layer on the surface of the source/drain region of the second electrode.

    Method of making a self-aligned silicide
    89.
    发明专利
    Method of making a self-aligned silicide 未知

    公开(公告)号：GB2328078B

    公开(公告)日：1999-07-14

    申请号：GB9716395

    申请日：1997-08-01

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

    Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

    IC production with embedded DRAM circuits and logic circuits on single chip
    90.
    发明专利
    IC production with embedded DRAM circuits and logic circuits on single chip 未知

    公开(公告)号：NL1007804C2

    公开(公告)日：1999-06-17

    申请号：NL1007804

    申请日：1997-12-16

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU HONG-JEN ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/768

    Abstract: Production of an IC component, with embedded DRAM circuits and logic circuits on a single substrate, involves (a) producing transfer FETs (104) in and on embedded DRAM circuit regions of the substrate (100); (b) producing logic FETs (120) in and on the logic circuit regions of the substrate (100); (c) forming a first insulating layer (136) on the transfer FETs (104) and on the logic FET (120)s; (d) defining first and second openings (146, 148) in the first insulating layer to expose the source/drain regions (138, 140) of at least one of the transfer FETs (104) and defining a third opening (150) to expose at least one conductor (134) within the logic circuit; (e) producing a first conductive layer (152) on the first insulating layer and within the openings for contacting one of the source/drain regions of a transfer FET (104), the conductive layer not filling the first opening (146); (f) producing a capacitor dielectric layer and then a second conductive layer within the first opening (146); and (g) patterning the conductive layers for laterally delimiting the upper and lower electrodes of a charge storage capacitor of an embedded DRAM.

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