公开(公告)号：JPH11191612A

公开(公告)日：1999-07-13

申请号：JP7378098

申请日：1998-03-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YO BUNKAN ,  YEW TRI-RUNG

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of leakage current in a capacitor by implanting a silicon layer with ions for converting it into a barrier layer and then forming a dielectric layer on the barrier layer after heat treatment and wet etching thereby, improving the quality of the dielectric layer. SOLUTION: An HSG layer 32 is formed on the surface of a conductive layer 30 using SiH4 and Si2 H6 as reaction gases, for example, and implanted with nitrogen ions. Thereafter, a thin barrier layer 34 of silicon oxynitride or silicon nitride, for example, is formed on the HSG layer 32 through rapid heating process. Since a thin native oxide layer 33 is formed on the surface of the barrier layer 34, this is removed through wet etching process. Subsequently, a dielectric layer 36 of tantalum oxide is formed on the surface of the battier layer 34 by LPCVD, followed by the formation of a top electrode layer 38 of titanium nitride on the surface of the dielectric layer 36.

公开(公告)号：JPH11163523A

公开(公告)日：1999-06-18

申请号：JP30448097

申请日：1997-11-06

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming multilayer interconnection structure, which has a landless via hole for interlayer connection and uses air as dielectric between the wirings. SOLUTION: A carbon layer is deposited on the surface of an insulator and a groove corresponding to a wiring pattern is formed on the surface of the carbon layer. A metal is supplied into the groove and onto the surface of the carbon layer, and a first layer wiring 66 is obtained by the subsequent chemical mechanical polishing process. Carbon ashing or etch back process is performed on the carbon layer, and the surface of the carbon layer is made lower than the wiring plane. An oxide capping layer 70 is formed on the wiring plane and on the surface of the recessed carbon layer. The carbon layer is consumed and removed by the oxidation process through the capping layer 70, and an air gap 74 is formed. Then, a silicon nitride etching stop layer 72 is formed on the surface of the capping layer 70, and a dielectric layer 76 is formed on the capping layer 70. After filing a via hole with a metal plug 78, a second layer wiring 80 is formed.

公开(公告)号：JPH11145383A

公开(公告)日：1999-05-28

申请号：JP29840997

申请日：1997-10-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method with which an integrated circuit device which can suppress the plasma damages of a gate electrode in an FET logic circuit, and at the same time, the polycrystalline silicon loss of the gate electrode can be made reduced. SOLUTION: An integrated circuit device is formed in such a way that protective layers 129 having shapes in match with that of a substrate are formed on a plurality of transfer FETs 104 and a logic FET 120, so that the film thicknesses of the layer 129 on a gate electrode 124 and source/drain regions 118 of the logic FET 120 become nearly equal to each other. Then the source/ drain regions 118 of one transfer FET 104 is exposed by forming a contact opening by removing a part of the protective layer 129, and a lower capacitor electrode 130 is formed so that the electrode 130 comes into contact with the source/drain regions 118. After the formation of the capacitor electrode 130, a charge storage capacitor with respect to the transfer FET is formed, by forming a capacitor dielectric layer 132 and an upper capacitor electrode 134 on the lower capacitor electrode 130. Thereafter, the protective layer 129 is removed from at least a part of its logic circuit region.

公开(公告)号：JPH11121616A

公开(公告)日：1999-04-30

申请号：JP27781497

申请日：1997-10-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To fill an unfilled via region, facilitate a gap filling process and prevent a void formation, by a method wherein a metal layer is deposited on wiring lines and in a gap between the wiring lines. SOLUTION: A dielectric material 40 is a silicon oxide layer or a borophosphosilicate glass layer, and a contact opening or via 44 is formed on a metal, polysilicon or an active region in a lower portion in a substrate 42. A first metal layer 46 uniformly fills the via 44 and the filled rear face is an aluminum or tungsten layer deposited so as to be flatted substantially to form a photoresist mask, and a first metal layer 46 is exposed and removed to make patterns of a wiring line. Next, an opening in the via is buried by deposition of a second metal layer to finish as a metal sidewalk spacer structure. Then, a remaining portion is extended to form a second sidewall structure to thereby prevent a void wherein contaminant accumulates from keing farmed.

公开(公告)号：JPH1196654A

公开(公告)日：1999-04-09

申请号：JP34325597

申请日：1997-12-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOREHIRO ,  KA YUKIMITSU

IPC: G11B19/04 ,  G11B7/09 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To provide a device capable of maintaining a data reading operation started from an accurate interrupted point after the occurrence of interruption by fetching information on which data frame is currently written in a memory means, instructing the memory means to discard the data frame, and arranging a laser pickup head in a data frame before the discarded data frame. SOLUTION: When an external vibration occurs to cause defocusing or miss- tracking in a laser pickup head during a reproducing operation, s servo circuit 600 generates a signal in a micro-controller 400 through a signal line 450. The micro-controller 400 changes an operation signal on a signal line 340 into a stop voltage state. At this time, a RAM and a time controller 370 fetch information on the micro-controller 400 fetches this information from the RAM and the time controller 370.

公开(公告)号：JPH1125615A

公开(公告)日：1999-01-29

申请号：JP27780797

申请日：1997-10-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： HUANG WEI-HUNG

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a main control circuit for CD(compact disk)-ROM drive capable of improving performance of a whole system by a DRAM working memory reducing an access frequency and reducing its cost by realizing the whole system as a one chip IC. SOLUTION: This control circuit is the control circuit for the CD-ROM drive used as a storage part of the digital data, and it reads out the data stored on a CD-ROM disk 401, and transfers the decoded data to a host computer system through an interface bus 450. Then, the control circuit is provided with CIRC (cross interleave Reed Solomon code) processor 500 and RSPC (Reed Solomon product like code)/EDC(error detection/correction) processor 600 connected to a bus interface controller 433 based on an ISO 9660 standard, and respective processors can access directly to a working memory device 440 connected to each other. Circuit constitution connected in such a manner reduces the access frequency in the working memory device, and eliminates a use of an internal high speed SRAM. Since the whole control circuit 400 is integrated into an IC device, the cost is reduced, and the performance is improved.

公开(公告)号：JPH10335662A

公开(公告)日：1998-12-18

申请号：JP21623597

申请日：1997-08-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KENTEI ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent current leakage, increase the sizes of a contact window and lessen a metal silicide in contact resistance and surface resistance, by taking advantage of a slope in a process where ions are diffused into source/drain regions of MOS components. SOLUTION: Self-aligned silicides each provided with an impurity diffusion region 29 are formed below source/drain regions 27 adjacent to isolation regions 24. This forming method comprises a step where ions are implanted, taking advantage of an angle of inclination. By this method, the source/drain regions 27 are increased in junction depth, and a metal silicide provided to the edge of the isolation region 24 is restrained from excessively approaching a source/ drain junction. The isolation regions 24 are subjected to over etching, whereby the surfaces of the isolation regions 24 are exposed. A metal silicide layer 31 is formed on the surfaces of the source/drain regions respectively, and a region used for the formation of a wide border contact window 34 is enlarged in area.

公开(公告)号：JPH10209397A

公开(公告)日：1998-08-07

申请号：JP1196497

申请日：1997-01-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHI WAY SAN ,  TORI RAN YUU ,  UOOTAA RUU

IPC: H01L27/04 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enhance a DRAM in capacitance using an HSG-Si layer in a process where the memory electrode of the DRAM is formed. SOLUTION: The capacitor of a DRAM cell is formed through such a manner that a doped polysilicon layer 30 is evaporated and then patterned so as to limit a lower electrode in breadth, and a hemispherical grained silicon(HSG-Si) first layer is formed on the doped polysilicon layer 30. The growth of the HSG-Si first layer is stopped, and then an HSG-Si second layer is grown. The growth of HSG-Si first layer is stopped by cooling down an evaporation substrate or by stopping evaporation for a certain time, and then evaporation is restarted for forming the HSG-Si second layer on the surface of the electrode. If the growth of the HSG-Si second layer is separately carried out independent of that of the HSG-Si first layer, the growth of the HSG-Si first layer may be interrupted by either cooling or suspending.

公开(公告)号：JPH10209303A

公开(公告)日：1998-08-07

申请号：JP17682597

申请日：1997-07-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a ROM device where problems such as lateral diffusion, junction leakage, drop of breakdown voltage, etc., do not occur, and provide further a manufacturing method. SOLUTION: This ROM device includes a semiconductor substrate, the first insulating layer made on the semiconductor substrate, and semiconductor layers 43a and 43b made on the first insulating layer. The semiconductor layers 43a and 43b are removed selectively so as to form a plurality of bit lines BL1 and BL2 arranged substantially in parallel in the first direction and a plurality of channel regions 50c and 50d arranged substantially in parallel in the second direction substantially orthogonal to the first direction, and the removed section forms a plurality of recesses. This ROM device further includes a plurality of second insulating layers made on those recesses, the third insulating layer covering the semiconductor layers 43a and 43b and those second insulating layers, and a plurality of conductive layers made on the third insulating layer and arranged substantially in parallel. Those conductive layers are arranged on the above channel regions 50c and 50d, substantially in the second direction.

公开(公告)号：JPH10200074A

公开(公告)日：1998-07-31

申请号：JP6837897

申请日：1997-03-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHI-CHUNG ,  CHEN TSAI-FU

IPC: C23C16/40 ,  C23C16/02 ,  C23C16/56 ,  H01G4/33 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture, in a low pressure environment, a capacitor dielectric body of a semiconductor memory device which has less leakage current. SOLUTION: First a semiconductor silicon substrate 10 having an electrode layer 11 made of NH3 -polysilicon nitride is made. Next, a tantalum oxide (Ta2 O5 ) film 12 is deposited all over the electrode layer 11. Then, the deposited tantalum oxide film is annealed at 800 deg.C for 30 minutes in a nitrogen gas (N2 O) atmosphere. By this post-deposition annealing method, a very reliable tantalum oxide film having less leakage current for a semiconductor memory device can be manufactured.