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    PRINTED CIRCUIT BOARD
    81.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20120261175A1

    公开(公告)日：2012-10-18

    申请号：US13156348

    申请日：2011-06-09

    Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

    Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

    IPC: H05K1/11

    CPC classification number: H05K1/0265 ,  H05K1/117 ,  H05K2201/0784 ,  H05K2201/09972

    Abstract: A printed circuit board includes a first circuit area, a second circuit area, a plurality of connectors, and a connecting terminal. The first circuit area is electrically connected to the second circuit area via the connectors. The connecting terminal is placed on one side of the first circuit area for electrically connecting with a load. An imaginary center line of the connecting terminal is perpendicular to the one side of the printed circuit board. The less a horizontal distance between the center line of connecting terminal and one of the connectors, the larger a vertical distance between the side of the printed circuit board and the one of the connector.

    Abstract translation: 印刷电路板包括第一电路区域，第二电路区域，多个连接器以及连接端子。 第一电路区域经由连接器电连接到第二电路区域。 连接端子位于第一电路区域的一侧，用于与负载电连接。 连接端子的假想中心线垂直于印刷电路板的一侧。 连接端子的中心线与其中一个连接器之间的水平距离越小，印刷电路板的侧面和连接器中的一个之间的垂直距离越大。

    Flat panel display and chip bonding pad
    82.
    发明授权
    Flat panel display and chip bonding pad 有权
    平板显示屏和芯片接合垫

    公开(公告)号：US08059249B2

    公开(公告)日：2011-11-15

    申请号：US12176416

    申请日：2008-07-21

    Applicant: Chun-Hsin Liu ,  Po-Yuan Liu

    Inventor： Chun-Hsin Liu ,  Po-Yuan Liu

    IPC: G02F1/1345

    CPC classification number: H05K1/025 ,  G02F1/1345 ,  G02F1/13452 ,  G02F2001/13456 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/0784 ,  H05K2201/09263 ,  H05K2201/10674

    Abstract: A flat panel display and a chip bonding pad thereof are provided. The flat panel display includes a display panel, an FPC board, first and second source driving chips, and a control circuit board. First and second wires in a peripheral circuit region of the display panel extend from the underneath of the FPC board to two opposite sides of the display panel and electrically connect the FPC board. The first source driving chips electrically connect the FPC board through parts of the first wires. The second source driving chips electrically connect the FPC board through the second wires. The chip bonding pad is under one of the first and second source driving chips. The chip bonding pad includes a first dielectric layer having first through holes and a second dielectric layer having second and third through holes arranged alternately. The second through holes correspond to the first through holes.

    Abstract translation: 提供了一种平板显示器及其芯片接合垫。 平板显示器包括显示面板，FPC基板，第一和第二源驱动芯片以及控制电路板。 显示面板的外围电路区域中的第一和第二导线从FPC板的下面延伸到显示面板的两个相对的两侧并将FPC基板电连接。 第一源驱动芯片通过部分第一导线将FPC板电连接。 第二源驱动芯片通过第二线电连接FPC板。 芯片接合焊盘位于第一和第二源极驱动芯片之一之下。 芯片接合焊盘包括具有第一通孔的第一介电层和具有交替布置的第二和第三通孔的第二介电层。 第二通孔对应于第一通孔。

    FAN-OUT UNIT AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE HAVING THE SAME
    83.
    发明申请
    FAN-OUT UNIT AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE HAVING THE SAME 有权
    扇出单元和薄膜晶体管阵列基板

    公开(公告)号：US20100155729A1

    公开(公告)日：2010-06-24

    申请号：US12637658

    申请日：2009-12-14

    Applicant: Sung-Hoon Yang ,  So-Woon Kim ,  Yeon-Ju Kim ,  So-Hyun Lee ,  Kwang-Hoon Lee ,  Mun-Soo Park ,  Jung-Hyeon Kim

    Inventor： Sung-Hoon Yang ,  So-Woon Kim ,  Yeon-Ju Kim ,  So-Hyun Lee ,  Kwang-Hoon Lee ,  Mun-Soo Park ,  Jung-Hyeon Kim

    IPC: H01L27/13 ,  H01L29/786

    CPC classification number: G02F1/1345 ,  H01L27/124 ,  H05K1/0265 ,  H05K1/167 ,  H05K2201/0784 ,  H05K2201/09263

    Abstract: A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.

    Abstract translation: 提出了一种能够控制具有高效空间利用的通道之间的电阻差的扇出单元和具有扇出单元的薄膜晶体管（TFT）阵列基板。 扇出单元包括：绝缘基板; 第一布线层，其形成在所述绝缘基板上并连接到焊盘; 第二布线层，其形成在绝缘基板上并连接到TFT; 以及电阻控制器，其连接在第一布线层和第二布线层之间，并且包括平行于第一布线层延伸的多个第一电阻器和垂直于第一电阻器延伸的多个第二电阻器，并交替地连接到第一电阻器 ，其中所述第一电阻器比所述第二电阻器长。

    ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE
    84.
    发明申请
    ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE 有权
    用于液晶显示装置的阵列基板

    公开(公告)号：US20090167654A1

    公开(公告)日：2009-07-02

    申请号：US12330720

    申请日：2008-12-09

    Applicant: Hyun-Chul Kim ,  Jin-Cheol Hong

    Inventor： Hyun-Chul Kim ,  Jin-Cheol Hong

    IPC: G09G3/36

    CPC classification number: G02F1/1345 ,  H01L27/124 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/0784 ,  H05K2201/09727 ,  H01L2924/00

    Abstract: An array substrate for a liquid crystal display device includes a substrate including a display area and a non-display area, the non-display area having a link area and a pad area, array elements in the display area on the substrate, first to nth pads in the pad area (n is a natural number), first to nth link lines in the link area and connected to the first to nth pads, respectively, wherein the first to (n/2−1)th link lines are symmetrical with the nth to (n/2+1)th link lines with respect to (n/2)th link line, the first to (n/2−1)th link lines have inclined portions, and the inclined portions of the first to kth link lines have decreasing widths and decreasing lengths toward the kth link line from the first link line, wherein k is larger than 1 and smaller than (n/2).

    Abstract translation: 一种液晶显示装置用阵列基板，具备包括显示区域和非显示区域的基板，所述非显示区域具有连接区域和焊盘区域，所述基板的显示区域中的阵列元件，第一至第n 焊盘区域中的焊盘（n是自然数），分别在链路区域中的第一至第n个链路线并分别连接到第一至第n个焊盘，其中第一到第（n / 2-1）个链路线与 第（n / 2）个连接线相对于第（n / 2）个连接线，第一至第（n / 2-1）个连接线具有倾斜部分，并且第一至第 第k个链路线具有从第一链路线到第k个链路线的宽度减小和长度减小，其中k大于1且小于（n / 2）。

    Fan-out wire structure
    87.
    发明申请
    Fan-out wire structure 有权
    扇出线结构

    公开(公告)号：US20070052895A1

    公开(公告)日：2007-03-08

    申请号：US11399344

    申请日：2006-04-07

    Applicant: Wan-Jung Chen

    Inventor： Wan-Jung Chen

    IPC: G02F1/1343

    CPC classification number: G02F1/1345 ,  G02F2201/12 ,  H05K1/0213 ,  H05K1/0265 ,  H05K1/167 ,  H05K2201/0326 ,  H05K2201/0352 ,  H05K2201/0784 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/10136

    Abstract: This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal layer and the second metal layer is formed on the first insulation layer, and the first metal layer and the second metal layer are electrically connected by a conductive material, so as to modulate the resistance of the fan-out wire structure by modulating the length of the second metal layer and the conductive material.

    Abstract translation: 本发明公开了一种用于显示装置的显示面板的扇出线结构。 扇出线结构包括第一金属层，第一绝缘层和第二金属层。 第一绝缘层形成在第一金属层上，第二金属层形成在第一绝缘层上，第一金属层和第二金属层通过导电材料电连接，以便调制电阻 通过调制第二金属层和导电材料的长度来实现扇出线结构。

    Method for optimizing a conductor-path layout for a print head of an ink printing device, and a conductor-path layout for such a print head
    88.
    发明授权
    Method for optimizing a conductor-path layout for a print head of an ink printing device, and a conductor-path layout for such a print head 失效
    用于优化墨水打印装置的打印头的导体路径布局的方法和用于这种打印头的导体路径布局

    公开(公告)号：US5400063A

    公开(公告)日：1995-03-21

    申请号：US992754

    申请日：1992-12-18

    Applicant: Andreas Kappel

    Inventor： Andreas Kappel

    IPC: B41J2/14 ,  H05K1/02 ,  B41J2/05

    CPC classification number: H05K1/0265 ,  B41J2/14072 ,  B41J2202/11 ,  H05K2201/0784 ,  H05K2201/09727

    Abstract: A substantially uniform and nevertheless low feed line resistance of the conductor paths (L.sub.i) can be realized for all heating elements in an ink jet printer by a suitable dimensioning of a transition structure (UV) of a conductor path layout disposed on a thin-film substrate. This transition structure connects the conductor paths of close spacing (LA) in the region of the heating elements (RH) to the conductor paths of wide spacing (LB) in the region of the bonding contacts to each other. For this purpose a dimensioning requirement is required, which in case of predetermined input values, i.e. the conductor path widths (d.sub.a, d.sub.b) and the separation distance widths (s.sub.a, s.sub.b) furnishes in the two regions and in the separation distance width (s.sub.v) of the transition structure (UV) as starting value the conductor width (d.sub.v) in the transition structure (UV).

    Abstract translation: 通过适当尺寸设置在薄膜上的导体路径布局的过渡结构（UV），可以实现对喷墨打印机中所有加热元件的导体路径（Li）的基本上均匀且仍然低的馈电线电阻 基质。 该过渡结构将在加热元件（RH）的区域中的紧密间隔（LA）的导体路径与接合触点的区域中的宽间距（LB）的导体路径彼此连接。 为此，需要尺寸要求，在预定的输入值的情况下，即导体路径宽度（da，db）和间隔距离宽度（sa，sb）在两个区域中提供并且在间隔距离宽度（sv ）作为过渡结构（UV）中的导体宽度（dv）作为起始值的过渡结构（UV）。

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