公开(公告)号：US20180263108A1

公开(公告)日：2018-09-13

申请号：US15870837

申请日：2018-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuaki TSUKUDA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H03H7/01

CPC classification number: H05K1/0216 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/023 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/0723 ,  H05K2201/09218 ,  H05K2201/093 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10151 ,  H05K2201/10689

Abstract: A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.

公开(公告)号：US20180042123A1

公开(公告)日：2018-02-08

申请号：US15231515

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

公开(公告)号：US09807877B1

公开(公告)日：2017-10-31

申请号：US15285593

申请日：2016-10-05

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd.

Inventor： Li-Kun Liu ,  Yan-Lu Li

IPC: H05K3/20 ,  H05K1/02 ,  H05K1/11 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/028 ,  H05K1/0393 ,  H05K1/115 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/427 ,  H05K3/4611 ,  H05K3/4655 ,  H05K3/4691 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09218 ,  H05K2203/063 ,  Y10T29/49128

Abstract: A flexible printed circuit board with multiple layers includes an inner wiring substrate and at least one outer wiring plate. Each outer wiring plate is connected to one surface of the inner wiring substrate, and defines at least one through hole which passes through the outer wiring plate to expose the inner wiring substrate. Each outer wiring plate further includes an adhesive plate connected to the inner wiring substrate. The adhesive plate includes a stepped portion extending towards a center of the through hole.

公开(公告)号：US20170257946A1

公开(公告)日：2017-09-07

申请号：US15602137

申请日：2017-05-23

Applicant: HE BEI SINOPACK ELECTRONIC TECH CO., LTD.

Inventor： Dongliang Zhao ,  Fei Ding ,  Linjie Liu

IPC: H05K1/03 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11 ,  H05K1/02 ,  H05K3/18

CPC classification number: H05K1/0306 ,  H01L23/13 ,  H05K1/0213 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/005 ,  H05K3/188 ,  H05K3/40 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2201/0723 ,  H05K2201/09218 ,  H05K2201/09618 ,  H05K2201/10303

Abstract: The present application discloses a method for fabricating ceramic insulator for electronic packaging, and relates to a technical field of outer shell packaging of electronic devices. Under the circumstance of using neither a chemical coating nor any bonding wire connection circuit, through a design that builds a electroplated circuit into the ceramic insulator, the method accomplishes coating of a nickel alloy protection layer onto a porcelain by an electroplating method, so that not only quality of a coating layer but also requirement of a complete appearance can be ensured. All circuits of the ceramic insulator fabricated by the aforesaid method can conduct with external circuits, such that the electroplating method can be used to accomplish coating of the nickel alloy layer, after accomplishment of all metal coating, metallization parts on an end surface of the porcelain is removed.

公开(公告)号：US09595217B2

公开(公告)日：2017-03-14

申请号：US14535216

申请日：2014-11-06

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Minghui Han

IPC: G09G3/20 ,  H05K1/02 ,  H05K1/11 ,  H01L23/66

CPC classification number: G09G3/20 ,  G09G2300/0404 ,  G09G2310/06 ,  G09G2310/08 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0242 ,  H05K1/0246 ,  H05K1/025 ,  H05K1/0296 ,  H05K1/11 ,  H05K2201/09218 ,  H05K2201/097 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2201/10128 ,  H01L2924/00

Abstract: A trace to be coupled to an input of a receiver, the trace including: a plurality of first portions; and a plurality of second portions alternately coupled in series with the first portions, the second portions having a width that is different from that of the first portions.

Abstract translation: 要耦合到接收器的输入的迹线，所述迹线包括：多个第一部分; 以及与第一部分交替耦合的多个第二部分，第二部分具有与第一部分不同的宽度。

公开(公告)号：US09538643B2

公开(公告)日：2017-01-03

申请号：US14245221

申请日：2014-04-04

Applicant: ROLLS-ROYCE PLC

Inventor： Claudio Zizzo

IPC: H05K1/02 ,  C08K3/04 ,  C08K7/06 ,  F02C7/00 ,  F01D5/28 ,  F01D17/24 ,  F01D25/24

CPC classification number: H05K1/0298 ,  C08K3/04 ,  C08K7/06 ,  F01D5/282 ,  F01D17/24 ,  F01D25/24 ,  F02C7/00 ,  F05D2300/224 ,  F05D2300/50 ,  F05D2300/6012 ,  F05D2300/603 ,  F05D2300/614 ,  H05K2201/09218 ,  Y02T50/672 ,  Y02T50/673

Abstract: A composite structure is provided. The structure is formed of rigid composite material in which non-metallic continuous fibers reinforce a polymer matrix. The continuous fibers are electrically conductive. The structure has electrodes electrically connected to the continuous fibers. The composite material contains one or more insulating barriers which electrically divide the structure so that a first portion of the material in electrical contact with one of the electrodes can be held at a different electrical potential to a second portion of the material in electrical contact with the other electrode. In use, an electrical unit can be provided to electrically bridge the first and second portions of the material such that electrical signals can be transmitted between the electrodes and the electrical unit via the continuous fibers.

Abstract translation: 提供复合结构。 该结构由刚性复合材料形成，其中非金属连续纤维增强聚合物基体。 连续纤维是导电的。 该结构具有电连接到连续纤维的电极。 复合材料包含一个或多个绝缘屏障，其将结构电分开，使得与电极之一电接触的材料的第一部分可以保持在与第二部分电接触的材料的不同电位 其他电极。 在使用中，可以提供电气单元以电气地桥接材料的第一和第二部分，使得电信号可以经由连续纤维在电极和电气单元之间传递。

公开(公告)号：US20160172286A1

公开(公告)日：2016-06-16

申请号：US14746247

申请日：2015-06-22

Applicant: Jin-Kyung KIM ,  Yong-hoon KIM ,  Seong-Ho SHIN

Inventor： Jin-Kyung KIM ,  Yong-hoon KIM ,  Seong-Ho SHIN

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/09218 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.

Abstract translation: 提供半导体封装，模块基板和具有该半导体封装的半导体封装模块。 半导体封装模块包括在其上表面上设置有多个信号线的模块基板，设置在模块基板上的封装基板，设置在封装基板的一个表面上的半导体芯片，以及设置在多个外部连接端子 在封装衬底的另一个表面上。

公开(公告)号：US20150366073A1

公开(公告)日：2015-12-17

申请号：US14764378

申请日：2014-01-30

Applicant: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM

Inventor： Shlomo MAGDASSI ,  Amir SHAPIRA ,  Michael LAYANI ,  Ido COOPERSTEIN

IPC: H05K3/12 ,  H05K1/02 ,  B29C67/00

CPC classification number: H05K3/125 ,  B22F1/0022 ,  B22F3/008 ,  B22F3/1055 ,  B29C64/112 ,  B29C64/135 ,  B29K2105/0002 ,  B29K2995/0005 ,  B33Y10/00 ,  B33Y70/00 ,  B33Y80/00 ,  C09D11/101 ,  C09D11/52 ,  H01B1/22 ,  H05K1/0296 ,  H05K1/097 ,  H05K3/1283 ,  H05K3/245 ,  H05K2201/09218 ,  H05K2203/1131 ,  H05K2203/1157 ,  H05K2203/1476 ,  Y02P10/295

Abstract: The invention generally relates to polymerizable conductive ink formulations comprising at least one metal source, at least one monomer and/or oligomer and a polymerization initiator, and uses thereof for printing three-dimensional functional structures. In particular a method of fabricating a three-dimensional conductive pattern on a substrate is disclosed, the method comprising: a) forming a pattern on a surface region of a substrate by using an ink comprising at least one metal source, at least one liquid polymerizable monomer and/or oligomer, and at least one polymerization initiator; b) polymerizing at least a portion of said liquid monomer and/or oligomer; c) rendering the metal source a continuous percolation path for electrical conductivity (sintering); d) repeating steps (a), (b) and optionally (c) to obtain a three-dimensional conductive pattern.

Abstract translation: 本发明一般涉及包含至少一种金属源，至少一种单体和/或低聚物和聚合引发剂的可聚合导电油墨配方及其用于印刷三维功能结构的用途。 特别地，公开了一种在衬底上制造三维导电图案的方法，所述方法包括：a）通过使用包含至少一种金属源的油墨，至少一种可聚合液体的液体形成图案，在基材的表面区域上形成图案 单体和/或低聚物，和至少一种聚合引发剂; b）聚合至少一部分所述液体单体和/或低聚物; c）使金属源具有连续的渗透路径用于导电（烧结）; d）重复步骤（a），（b）和任选地（c）以获得三维导电图案。

公开(公告)号：US20150085456A1

公开(公告)日：2015-03-26

申请号：US14032235

申请日：2013-09-20

Applicant: Ronald Steven Cok

Inventor： RONALD STEVEN COK

IPC: H05K1/02

CPC classification number: H05K1/0274 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0289 ,  H05K1/0298 ,  H05K1/097 ,  H05K1/185 ,  H05K3/1258 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/09218 ,  H05K2203/0108

Abstract: An imprinted multi-level micro-wire structure includes a substrate and a first layer formed over the substrate. The first layer includes first micro-wires formed in first micro-channels imprinted in the first layer. A second layer is formed in contact with the first layer. The second layer includes second micro-wires formed in second micro-channels imprinted in the second layer. At least one of the second micro-wires is in electrical contact with at least one of the first micro-wires.

Abstract translation: 印刷的多级微线结构包括基板和形成在基板上的第一层。 第一层包括形成在第一层中的第一微通道中形成的第一微细线。 形成与第一层接触的第二层。 第二层包括在第二层中印刷的第二微通道中形成的第二微细线。 第二微线中的至少一个与第一微线中的至少一个电接触。