公开(公告)号：WO2007106642A3

公开(公告)日：2007-11-29

申请号：PCT/US2007062376

申请日：2007-02-19

Applicant: MOTOROLA INC ,  SAVIC JOVICA ,  CHELINI REMY J ,  DUNN GREGORY J

Inventor： SAVIC JOVICA ,  CHELINI REMY J ,  DUNN GREGORY J

IPC: H05K1/16

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2203/025 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract translation: 公开了一种在印刷电路板上形成嵌入式电容器的方法。 电容器通过在位于PCB上的一个或多个电极上沉积第一电介质层而形成在印刷电路板上。 另一个电极形成在第一电介质层的顶部上并且第二电介质层沉积在该电极的顶部上。 第三电极形成在第二介电层的顶部上。 两个电介质层通过诸如喷砂的方法在一个步骤中被磨蚀地描绘以限定第一和第二电介质层的部分以形成多层电容结构。

公开(公告)号：WO2007078947A2

公开(公告)日：2007-07-12

申请号：PCT/US2006048473

申请日：2006-12-19

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  MAGERA JAROSLAW A ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  MAGERA JAROSLAW A ,  SAVIC JOVICA

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

Abstract translation: 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入的电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

公开(公告)号：WO2006101638A2

公开(公告)日：2006-09-28

申请号：PCT/US2006005839

申请日：2006-02-17

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

Inventor： DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

IPC: B44C1/22 ,  C23F1/00

CPC classification number: C23F1/40 ,  C23F1/02 ,  C23F1/32 ,  C23F1/34 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/025 ,  H05K3/06 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0746

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

Abstract translation: 公开了一种用于制造图案化的嵌入式电容层的方法。 该方法包括制造覆盖在印刷电路衬底（505）上的导电金属层（515）上的陶瓷氧化物层（510），在区域（705）内穿孔（1320）陶瓷氧化物层，以及去除 （1325）通过化学蚀刻导电金属层的区域中的陶瓷氧化物层和导电金属层。 陶瓷氧化物层可以小于1微米厚。

公开(公告)号：WO2007078947A3

公开(公告)日：2007-07-12

申请号：PCT/US2006/048473

申请日：2006-12-19

Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica

Inventor： DUNN, Gregory, J. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica

IPC: H05K1/11

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

公开(公告)号：WO2006101638A3

公开(公告)日：2006-09-28

申请号：PCT/US2006/005839

申请日：2006-02-17

Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  CROSWELL, Robert, T. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica ,  TUNGARE, Aroon, V.

Inventor： DUNN, Gregory, J. ,  CROSWELL, Robert, T. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica ,  TUNGARE, Aroon, V.

IPC: H01L21/302

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

公开(公告)号：WO2005062803A2

公开(公告)日：2005-07-14

申请号：PCT/US2004/042529

申请日：2004-12-17

Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  CROSWELL, Robert, T. ,  DEAN, Timothy, B. ,  GAMBOA, Claudia, V. ,  SAVIC, Jovica

Inventor： DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  CROSWELL, Robert, T. ,  DEAN, Timothy, B. ,  GAMBOA, Claudia, V. ,  SAVIC, Jovica

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/42

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (> 1000 pf/mm²).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器。

公开(公告)号：WO2004109719A2

公开(公告)日：2004-12-16

申请号：PCT/US2004/014665

申请日：2004-05-11

Applicant: MOTOROLA, INC. , A CORPORATION OF THE STATE OF DELAWARE ,  DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  SAVIC, Jovica

Inventor： DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  SAVIC, Jovica

IPC: H01C

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

Abstract: A printed circuit polymer thick film (PTF) resistor (410, 420) includes tolerance control material (425, 426, 440) that substantially surrounds the resistor body (423) and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment (420), the tolerance control material is the same metallic material as the printed circuit conductors (430), and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad (435) of the resistor. A layout cell (700) is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

Abstract translation: 印刷电路聚合物厚膜（PTF）电阻器（410,420）包括基本上围绕电阻体（423）的公差控制材料（425,426,440），并显着地改善了电阻与电阻器长度的线性度，并显着地降低 电阻 - 电阻和板对板制造方差。 在一个实施例（420）中，公差控制材料是与印刷电路导体（430）相同的金属材料，并且形成在电阻器主体的每一侧上的两个指形图案中，每个指形图案连接到一个端子焊盘（435 ）的电阻。 布局单元（700）用于制造PTF电阻。 一种制造PTF电阻的方法。

公开(公告)号：WO2013009738A1

公开(公告)日：2013-01-17

申请号：PCT/US2012/046039

申请日：2012-07-10

Applicant: CISCO TECHNOLOGY, INC ,  SAVIC, Jovica ,  YANG, Zhiping ,  XUE, Jie ,  LI, Li

Inventor： SAVIC, Jovica ,  YANG, Zhiping ,  XUE, Jie ,  LI, Li

IPC: H01L23/498 ,  H01L23/50 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10454 ,  H05K2203/1469

Abstract: A cavity is formed in a support structure, the support structure being operable to support a semiconductor device, and at least a portion of a circuit element is disposed within the cavity in the support structure. The cavity in the support structure is filled with an electrically non- conductive filling material so as to at least partially surround the circuit element with the non- conductive filling material, and the semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract translation: 空腔形成在支撑结构中，支撑结构可操作以支撑半导体器件，并且电路元件的至少一部分设置在支撑结构内的空腔内。 支撑结构中的空腔填充有非导电填充材料，以至少部分地围绕电路元件与非导电填充材料，并且半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。

公开(公告)号：WO2007100948A3

公开(公告)日：2008-07-10

申请号：PCT/US2007061218

申请日：2007-01-29

Applicant: MOTOROLA INC ,  TUNGARE AROON V ,  ELIACIN MANES ,  HWANG LIH-TYNG ,  LEMPKOWSKI ROBERT B ,  LIU JUNHUA ,  SAVIC JOVICA

Inventor： TUNGARE AROON V ,  ELIACIN MANES ,  HWANG LIH-TYNG ,  LEMPKOWSKI ROBERT B ,  LIU JUNHUA ,  SAVIC JOVICA

IPC: H01P1/10

CPC classification number: H01G5/16 ,  H01G5/011 ,  H01H59/0009

Abstract: A first and second capacitor plate are provided (101 and 102). Each capacitor plate has an opening disposed therethrough with the second capacitor plate being disposed substantially opposite the first capacitor plate. A first electrically conductive path interface is then disposed (103) in one of these openings as is at least a second electrically conductive path interface (104).

Abstract translation: 提供第一和第二电容器板（101和102）。 每个电容器板具有通过其设置的开口，第二电容器板与第一电容器板基本相对设置。 然后，至少第二导电路径接口（104）将第一导电路径接口（103）设置在这些开口之一中。

公开(公告)号：WO2007106642A2

公开(公告)日：2007-09-20

申请号：PCT/US2007/062376

申请日：2007-02-19

Applicant: MOTOROLA, INC. ,  SAVIC, Jovica, ,  CHELINI, Remy J., ,  DUNN, Gregory J.,

Inventor： SAVIC, Jovica, ,  CHELINI, Remy J., ,  DUNN, Gregory J.,

IPC: H01G7/00 ,  H01K3/10

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2203/025 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract translation: 公开了一种在印刷电路板上形成嵌入式电容器的方法。 通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。 另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。 在第二电介质层的顶部形成第三电极。 通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。