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公开(公告)号：KR1020130081749A
公开(公告)日：2013-07-18
申请号：KR1020120002726
申请日：2012-01-10
Applicant: 서울대학교산학협력단 , 국민대학교산학협력단
IPC: H01L21/31
CPC classification number: H01L21/76843 , H01L21/28556 , H01L21/288 , H01L21/76877 , H01L21/76898
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to secure an even step coverage property by using a self-assembled monolayer. CONSTITUTION: A barrier layer (120) comprises a Mercapto Propyl Tri Methoxy Silane (MPTMS). The barrier layer comprises a monomolecular film. The MPTMS is formed on a substructure (110). A conductive layer (130) is formed on the barrier layer. The conductive layer comprises a copper.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过使用自组装单层来确保均匀阶梯覆盖性。 构成：阻挡层（120）包含巯基丙基三甲氧基硅烷（MPTMS）。 阻挡层包含单分子膜。 MPTMS形成在子结构（110）上。 导电层（130）形成在阻挡层上。 导电层包括铜。
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公开(公告)号：KR101652342B1
公开(公告)日：2016-08-30
申请号：KR1020140079976
申请日：2014-06-27
Applicant: 국민대학교산학협력단
IPC: H01L31/0236 , H01L31/036
CPC classification number: Y02E10/50
Abstract: 태양전지표면의택스처링방법에관한것이다.
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公开(公告)号：KR1020160001437A
公开(公告)日：2016-01-06
申请号：KR1020140079976
申请日：2014-06-27
Applicant: 국민대학교산학협력단
IPC: H01L31/0236 , H01L31/036
CPC classification number: Y02E10/50 , H01L31/0236 , H01L31/02363 , H01L31/036
Abstract: 본원은, 태양전지표면의택스처링방법을제공한다.
Abstract translation: 本发明提供了一种用于纹理化太阳能电池表面的方法。 用于纹理化太阳能电池表面的方法包括以下步骤：在基板上施加光致抗蚀剂; 通过使用具有重复图案的模具在基板上形成图案，并固化图案; 并蚀刻衬底。 根据本发明，当纹理化太阳能电池的表面时，该方法通过使用压印或光刻来在基板上形成光致抗蚀剂。 此时，该方法通过使用纹理化来增加基板表面曝光单元的面积，从而降低反射率并提高太阳能电池效率。
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4.发明公开나노 임프린팅과 포토 리소그래피 방법을 동시에 이용한 몰드 제조 방법, 및 상기 방법에 의하여 제조된 몰드를 이용한 미세 패턴 형성 방법 无效使用纳米印刷和光刻技术制造模具的方法以及使用模具形成精细图案的方法
公开(公告)号：KR1020120111306A
公开(公告)日：2012-10-10
申请号：KR1020110029725
申请日：2011-03-31
Applicant: 국민대학교산학협력단
CPC classification number: G03F7/0002 , G03F7/16 , G03F7/162 , G03F7/325 , G03F7/70616 , H01L21/0228 , H01L21/0273 , H01L21/0337
Abstract: PURPOSE: A manufacturing method of a mold, the mold, and a forming method of fine patterns using the mold are provided to reduce costs needed for manufacturing processes and to form nano-sized line patterns on a substrate. CONSTITUTION: A manufacturing method of a mold includes the following: a first pattern is formed on a substrate(210) using ultraviolet ray shielding materials; a molding resin is applied on the substrate; a mask mold with a second pattern is pressurized on the substrate with the molding resin in order to arrange a surface which is shared by the first pattern and the second pattern; the patterns are imprinted; the molding resin is cured; and the master mold is removed from the substrate.
Abstract translation: 目的：提供使用该模具的模具的制造方法，模具和精细图案的成形方法，以降低制造工艺所需的成本并在基板上形成纳米尺寸的线图案。 构成：模具的制造方法包括：使用紫外线屏蔽材料在基板（210）上形成第一图案; 将模塑树脂施加在基材上; 为了布置由第一图案和第二图案共享的表面，具有第二图案的掩模模具用模制树脂在基板上加压; 图案印记; 成型树脂固化; 并将主模从衬底上移除。
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公开(公告)号：KR1020120111288A
公开(公告)日：2012-10-10
申请号：KR1020110029693
申请日：2011-03-31
Applicant: 국민대학교산학협력단
CPC classification number: G03F7/0002 , G03F7/16 , G03F7/325 , H01L21/0273 , H01L21/0337 , H01L21/31144
Abstract: PURPOSE: A fine pattern forming method with a photo mask and a nano-imprinting mold is provided to form patterns of various shapes and to form nano-sized line patterns by using micro-sized line patterns. CONSTITUTION: A fine pattern forming method includes the following: Pattern forming resist(120) is applied on a substrate(110); a master mold with a first pattern is in contact with the upper side of the pattern forming resist; the master mold is pressurized to be imprinted; the master mold is irradiated with ultraviolet rays through a photo-mask with a second pattern which is different from the first pattern; and the master mold and the photo-mask are separated from the substrate to develop the pattern forming resist.
Abstract translation: 目的：提供具有光掩模和纳米压印模具的精细图案形成方法，以形成各种形状的图案，并通过使用微尺寸线图案形成纳米尺寸线图案。 构成：精细图案形成方法包括：图案形成抗蚀剂（120）施加在基板（110）上; 具有第一图案的母模与图案形成抗蚀剂的上侧接触; 主模具加压压印; 通过具有不同于第一图案的第二图案的光掩模用紫外线照射母模; 并且将母模和光掩模与基板分离以形成图案形成抗蚀剂。
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Patent Agency Ranking
公开(公告)号：KR1020110044633A
公开(公告)日：2011-04-29
申请号：KR1020090101416
申请日：2009-10-23
Applicant: 엘지디스플레이 주식회사 , 국민대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L29/66742 , H01L29/45 , H01L29/7869
Abstract: PURPOSE: A method for manufacturing a thin film transistor using a single copper target and thin film transistor using the method are provided to perform a sputtering process by copper or a single copper alloy target, thereby providing a thin fill transistor which forms a source and a drain by copper or copper alloy. CONSTITUTION: A gate electrode(105) is formed on a glass substrate(101). A gate insulating film(107), a semiconductor layer(117), and an ohmic contact layer(119) are deposited on the gate electrode. A natural oxide film is formed on the ohmic contact layer. An oxide film(115) is deposited on the ohmic contact layer using metal including copper. A source-drain layer(121) is deposited on the oxide film using metal including the copper.
Abstract translation: 目的：提供使用该方法制造使用单个铜靶和薄膜晶体管的薄膜晶体管的方法，以通过铜或单一铜合金靶进行溅射处理，由此提供形成源极和/ 用铜或铜合金排水。 构成：在玻璃基板（101）上形成栅电极（105）。 栅极绝缘膜（107），半导体层（117）和欧姆接触层（119）沉积在栅电极上。 在欧姆接触层上形成自然氧化膜。 氧化膜（115）使用包括铜的金属沉积在欧姆接触层上。 源极 - 漏极层（121）使用包含铜的金属沉积在氧化膜上。
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公开(公告)号：KR1020100107905A
公开(公告)日：2010-10-06
申请号：KR1020090026250
申请日：2009-03-27
Applicant: 국민대학교산학협력단
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/04 , G11C13/0004 , H01L29/517
Abstract: PURPOSE: A ReRAM device and a manufacturing method thereof are provided to improve the interfacial property and memory property of a ReRAM device by forming a second electrode layer pattern after forming an adhesive patter between the second electrode pattern and a metal oxide layer. CONSTITUTION: A substrate(100) comprises a substrate insulating layer(120) and a substrate body layer(110). A first electrode layer(200) is formed on the substrate. A metal oxide layer(300) is formed on the first electrode layer. A self-assembled monolayer, which includes an aperture pattern exposing the metal oxide layer, is formed on the metal oxide layer. A second electrode layer pattern(500) is formed on the metal oxide layer.
Abstract translation: 目的：提供ReRAM器件及其制造方法，以通过在形成第二电极图案和金属氧化物层之间的粘合剂图案之后形成第二电极层图案来改善ReRAM器件的界面特性和存储特性。 构成：衬底（100）包括衬底绝缘层（120）和衬底主体层（110）。 在基板上形成第一电极层（200）。 在第一电极层上形成金属氧化物层（300）。 在金属氧化物层上形成包括露出金属氧化物层的孔径图案的自组装单层。 在金属氧化物层上形成第二电极层图案（500）。
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8.发明授权
公开(公告)号：KR100979190B1
公开(公告)日：2010-08-31
申请号：KR1020080037274
申请日：2008-04-22
Applicant: 국민대학교산학협력단
IPC: H01L27/115 , H01L21/8247 , B82Y10/00
Abstract: 본 발명은 자기조립단분자막을 이용하여 증착 형성한 금속 나노크리스탈에 의해 전하를 저장하는 플래쉬 메모리의 플로팅 게이트를 형성하기 위한 플로팅 게이트 형성방법, 이를 이용한 비휘발성 메모리 장치 및 그 제조방법에 관한 것으로, 반도체 기판 상에 플로팅 게이트를 형성하는 방법은 반도체 기판 상에 터널링 산화막을 형성하는 단계와, 상기 터널링 산화막 상에 자기조립 방식으로 조립되는 자기조립단분자막(self-assembled monolayers, SAMs)으로서 금속 나노 크리스탈과 이온결합이 이루어질 수 있는 결합기를 제공하며 다수의 금속 나노 크리스탈이 터널링 산화막으로 확산되는 것을 방지하기 위한 씨드층(seed layer)을 형성하는 단계와, 상기 씨드층(seed layer) 위에 불연속적인 입자형태로 증착되어 전하를 저장하는 다수의 금속 나노크리스탈을 형� �하는 단계를 포함하는 것을 특징으로 한다.
플래쉬 메모리, 플로팅 게이트, SAMs, 금속 나노크리스탈, 증착-
公开(公告)号：KR1020080088214A
公开(公告)日：2008-10-02
申请号：KR1020070030850
申请日：2007-03-29
Applicant: 국민대학교산학협력단
IPC: H01L21/8247 , H01L27/115 , B82Y10/00
CPC classification number: H01L29/42324 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/66825
Abstract: A method for forming a floating gate, a non-volatile memory device, and a manufacturing thereof are provided to prevent a property change of layer quality due to a high-temperature heat treatment process by forming a nano crystal with a micell. A tunneling oxide layer(11) is formed on an upper surface of a semiconductor substrate(10). A nano structure is formed on the tunneling oxide layer by using a self-assembly method. A gate forming solution including a micell template is coated on the nano structure. A precursor material for synthesizing metal salt is introduced into the nano structure. A floating gate is formed by arranging the metal salt on the tunneling oxide layer by removing the micell template on the semiconductor substrate.
Abstract translation: 提供一种用于形成浮动栅极，非易失性存储器件及其制造的方法，以通过用胶束形成纳米晶体来防止由于高温热处理工艺引起的层质量的性质变化。 隧道氧化物层（11）形成在半导体衬底（10）的上表面上。 通过使用自组装方法在隧道氧化物层上形成纳米结构。 包含胶束模板的浇口形成溶液涂覆在纳米结构上。 将用于合成金属盐的前体材料引入纳米结构。 通过去除半导体衬底上的胶束模板，将金属盐布置在隧道氧化物层上形成浮栅。
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公开(公告)号：KR101326711B1
公开(公告)日：2013-11-08
申请号：KR1020120002726
申请日：2012-01-10
Applicant: 서울대학교산학협력단 , 국민대학교산학협력단
IPC: H01L21/31
Abstract: 본 발명은 신뢰성이 향상된 반도체 소자 및 그 제조방법을 위하여, 하부 구조체, 하부 구조체 상에 형성된 MPTMS(mercaptopropyltrimethoxysilane)를 포함하는 장벽층, 장벽층 상에 형성된 도전층을 포함하는, 반도체 소자 및 그 제조방법이 제공된다.
Abstract translation: 对于可靠性，本发明是改进的半导体器件及其制造方法，所述下部结构的方法，其包括形成在其下的结构，包括形成在所述阻挡层中，半导体器件及其制造的方法上的导电层的MPTMS（巯基丙基）的势垒层 等等。
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