公开(公告)号：KR1020080020963A

公开(公告)日：2008-03-06

申请号：KR1020070088261

申请日：2007-08-31

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 하세베가즈히데 ,  주파오-화 ,  우메자와고오따 ,  가도나가겐따로오 ,  장패리

IPC: H01L21/205

CPC classification number: C23C16/45525 ,  C03C17/225 ,  C03C2217/281 ,  C03C2217/282 ,  C03C2217/283 ,  C03C2218/152 ,  C23C16/30 ,  C23C16/45542 ,  C23C16/45546 ,  C23C16/45578

Abstract: A method for forming a layer for a semiconductor process is provided to form an insulation layer with a predetermined thickness by relatively reducing an etch rate in a cleaning process even if a layer is formed at a relatively low temperature. In a first process, first process gas and foregoing gas as one of third and fourth process gases with respect to a process region are supplied while second process gas and following gas as the other of the third and fourth process gases with respect to the process region stop their supply. While the following gas with respect to the process region is supplied, the supply of the foregoing gas and the second process gas with respect to the process region is stopped in a second process. While the second process gas with respect to the process region is supplied, the supply of the first process gas with respect to the process region is stopped in a third process. A cycle alternately including first, second and third processes is repeated several times so that thin films stacked by the cycle are stacked to form an insulation layer with a predetermined thickness. Each cycle can include an intervening process between the second and third processes so that the process region is exhausted while the supply of the first, second, third and fourth process gases with respect to the process region is stopped.

Abstract translation: 提供一种用于形成半导体工艺的层的方法，即使在相对低的温度下形成层，通过相对地减少清洁过程中的蚀刻速率来形成具有预定厚度的绝缘层。 在第一过程中，相对于处理区域，第一工艺气体和作为第三和第四工艺气体之一的前述气体相对于工艺区域被供给，而第二工艺气体和随后的气体作为第三和第四工艺气体中的另一个相对于工艺区域 停止供应 虽然提供了相对于处理区域的以下气体，但是在第二过程中停止了相对于处理区域的上述气体和第二工艺气体的供应。 当提供相对于处理区域的第二工艺气体时，在第三工序中停止相对于工艺区域的第一工艺气体的供给。 交替地包括第一，第二和第三工艺的循环重复几次，使得通过循环堆叠的薄膜被堆叠以形成具有预定厚度的绝缘层。 每个循环可以包括在第二和第三过程之间的中间过程，使得处理区域被耗尽，同时停止相对于处理区域的第一，第二，第三和第四工艺气体的供给。

公开(公告)号：KR101242274B1

公开(公告)日：2013-03-12

申请号：KR1020090032026

申请日：2009-04-14

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 가도나가겐따로오 ,  도네가와야마또 ,  주파오화 ,  하세베가즈히데 ,  시바따데쯔야

IPC: H01L21/205

CPC classification number: H01L21/3185 ,  H01L21/02145 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/28282 ,  H01L21/31612 ,  H01L29/792

Abstract: 반도체 처리용 성막 방법은, 실리콘 소스 가스와 금속 소스 가스가 선택적으로 공급 가능한 처리 용기의 처리 영역 내에서, 피처리 기판 상에 금속 도프된 실리콘 함유 절연막을 형성하는 성막 처리를 행한다. 성막 처리는 상기 금속 소스 가스의 공급의 차단을 유지하는 동시에, 상기 실리콘 소스 가스를 화학적으로 반응시켜 제1 절연 박층을 형성하는 공정과, 다음에 상기 실리콘 소스 가스의 공급의 차단을 유지하는 동시에, 상기 금속 소스 가스를 화학적으로 반응시켜 제1 금속 박층을 형성하는 공정과, 다음에 상기 금속 소스 가스의 공급의 차단을 유지하는 동시에, 상기 실리콘 소스 가스를 화학적으로 반응시켜 제2 절연 박층을 형성하는 공정을 구비한다.
절연 박층, 금속 박층, 실리콘 소스 가스, 금속 소스 가스, 성막 장치

公开(公告)号：KR101140069B1

公开(公告)日：2012-04-30

申请号：KR1020070088261

申请日：2007-08-31

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 하세베가즈히데 ,  주파오-화 ,  우메자와고오따 ,  가도나가겐따로오 ,  장패리

IPC: H01L21/205

CPC classification number: C23C16/45525 ,  C03C17/225 ,  C03C2217/281 ,  C03C2217/282 ,  C03C2217/283 ,  C03C2218/152 ,  C23C16/30 ,  C23C16/45542 ,  C23C16/45546 ,  C23C16/45578

Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas or oxynitriding gas, a third process gas containing a boron-containing gas, and a fourth process gas containing a carbon hydride gas. A first step performs supply of the first process gas and a preceding gas, which is one of the third and fourth process gases, while stopping supply of the second process gas and a succeeding gas, which is the other of the third and fourth process gases. A second step performs supply of the succeeding gas, while stopping supply of the second process gas and the preceding gas. A third step performs supply of the second process gas while stopping supply of the first process gas.

公开(公告)号：KR1020090110786A

公开(公告)日：2009-10-22

申请号：KR1020090032026

申请日：2009-04-14

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 가도나가겐따로오 ,  도네가와야마또 ,  주파오화 ,  하세베가즈히데 ,  시바따데쯔야

IPC: H01L21/205

CPC classification number: H01L21/3185 ,  H01L21/02145 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/28282 ,  H01L21/31612 ,  H01L29/792

Abstract: PURPOSE: A film forming method for a semiconductor process is provided to control metal concentration in forming a metal doped insulation film including silicon. CONSTITUTION: While supply of a metal source gas is blocked, a first insulation film is formed by chemically reacting to a silicon source gas(S1). While supply of the silicon source gas is blocked, a first metal film is formed by chemically reacting to the metal source gas(S2). While supply of the metal source gas is blocked, a second insulation film is formed by chemically reacting to the silicon source gas(S3). The first insulation film, the first metal film, and the second insulation film are successively laminated.

Abstract translation: 目的：提供一种用于半导体工艺的成膜方法，以在形成包括硅的金属掺杂绝缘膜的过程中控制金属浓度。 构成：当金属源气体的供给被阻塞时，通过与硅源气体（S1）发生化学反应形成第一绝缘膜。 当硅源气体的供给被阻塞时，通过与金属源气体化学反应形成第一金属膜（S2）。 当金属源气体的供给被阻挡时，通过与硅源气体化学反应形成第二绝缘膜（S3）。 第一绝缘膜，第一金属膜和第二绝缘膜依次层叠。