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公开(公告)号：KR101044133B1
公开(公告)日：2011-06-24
申请号：KR1020090112028
申请日：2009-11-19
Applicant: 삼성전기주식회사
Abstract: 본 발명은 인쇄회로기판 제조용 캐리어에 관련되며, 2층의 금속층, 및 상기 2층의 금속층에 적층된 절연층을 포함하는 베이스부재, 및 상기 베이스부재의 측면에 형성된 접착부재를 포함한다.
또한, 본 발명은 인쇄회로기판 제조용 캐리어의 제조방법 및 상기 캐리어를 이용한 인쇄회로기판의 제조방법에 관련된다.
캐리어, 접착부재, 빌드업층-
公开(公告)号：KR1020110060623A
公开(公告)日：2011-06-08
申请号：KR1020090117252
申请日：2009-11-30
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A carrier member for manufacturing a substrate as an insulating layer and a circuit pattern of a coreless substrate and a method for manufacturing a substrate using the same are provided to save the manufacturing cots of a coreless substrate. CONSTITUTION: Metal layers(120) are placed on both sides of an insulating layer(110). A first hole(130) penetrates an edge of the insulating layer in a thickness direction. A fixing member(140) is inserted into the first hole and fixes two insulating layers. A base substrate is placed between the insulating layers. A second hole is formed on the base substrate. The second hole corresponds to the first hole.
Abstract translation: 目的：提供用于制造作为绝缘层的基板的载体部件和无芯基板的电路图案以及使用其的基板的制造方法，以节省无芯基板的制造单元。 构成：将金属层（120）放置在绝缘层（110）的两侧。 第一孔（130）在厚度方向上穿透绝缘层的边缘。 固定构件（140）插入到第一孔中并固定两个绝缘层。 将基底放置在绝缘层之间。 在基底基板上形成第二孔。 第二个孔对应于第一个孔。
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公开(公告)号：KR1020110055133A
公开(公告)日：2011-05-25
申请号：KR1020090112028
申请日：2009-11-19
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A carrier for manufacturing a printed circuit board and manufacturing method thereof are provided to configure a carrier by a part of a printed circuit board, thereby preventing cost loss due to the manufacture of the carrier. CONSTITUTION: A base member functions as a core layer. The base member includes a two-layered metal layer(120) and an insulating layer(110). An adhesive member(200) adheres the two-layered metal layer. The length of the adhesive member is thicker than the thickness of the base member to form a step toward the insulating layer. The adhesive member comprises a protrusion in the thickness direction of the base member.
Abstract translation: 目的：制造印刷电路板的载体及其制造方法，由印刷电路板的一部分构成载体，由此防止由于载体的制造造成的成本损失。 构成：基础成员充当核心层。 基底构件包括双层金属层（120）和绝缘层（110）。 粘合剂（200）粘附双层金属层。 粘合剂部件的长度比基体部件的厚度厚，以形成朝向绝缘层的台阶。 粘合构件包括在基底构件的厚度方向上的突起。
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公开(公告)号：KR101022914B1
公开(公告)日：2011-03-16
申请号：KR1020080108849
申请日：2008-11-04
Applicant: 삼성전기주식회사
Abstract: 본 발명은 인쇄회로기판의 제조방법에 관한 것으로서, 절연층과 제1금속층을 갖는 베이스 기판의 제1금속층을 패터닝하여 윈도우를 형성한 후, 플라즈마 에칭을 통해서 상기 윈도우에 의해 노출된 부위의 절연층을 에칭하여 회로용 홈 및 블라인드 비아홀을 형성하고, 이어서 상기 회로용 홈 및 블라인드 비아홀에 제2금속층을 충전하여 회로패턴 및 블라인드 비아를 형성하는 것을 특징으로 한다.
인쇄회로기판, 플라즈마 에칭, 회로패턴, 블라인드 비아홀Abstract translation: 一种制造印刷电路板的方法，该方法包括：通过图案化具有绝缘层和第一金属层的基础衬底的第一金属层来形成窗口; 并且通过用第二金属层填充电路凹槽和盲孔以形成电路图案和盲孔。
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公开(公告)号：KR1020090086830A
公开(公告)日：2009-08-14
申请号：KR1020080012317
申请日：2008-02-11
Applicant: 삼성전기주식회사
IPC: H05K3/42
CPC classification number: H05K3/421 , H05K1/115 , H05K3/0047 , H05K2201/09545
Abstract: A method for manufacturing a printed circuit board is provided to reduce the number of manufacturing processes and a manufacturing cost by forming a pattern and a via in a conductive material forming process. A circuit pattern and a via land are formed in an inner layer substrate(S100). An insulating material is laminated on the inner layer(S200). The via hole is formed to pass through the inner layer substrate and the insulating material(S300). A seed layer is formed in an inner wall of the insulating material, the inner wall of the via hole, and the inner wall of the blind via hole(S400). A plating resist is formed in the seed layer(S500). The conductive material is formed in the surface of the seed layer, the inner part of the blind via hole, and the inner part of the via hole(S600). The plating resist is removed(S700).
Abstract translation: 提供一种制造印刷电路板的方法，通过在导电材料形成工艺中形成图案和通孔来减少制造工艺的数量和制造成本。 在内层基板中形成电路图案和通孔焊盘（S100）。 在内层层叠绝缘材料（S200）。 通孔形成为穿过内层基板和绝缘材料（S300）。 种子层形成在绝缘材料的内壁，通孔的内壁和盲孔的内壁（S400）中。 在种子层中形成电镀抗蚀剂（S500）。 导电材料形成在种子层的表面，盲孔的内部和通孔的内部（S600）。 去除电镀抗蚀剂（S700）。
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Patent Agency Ranking
公开(公告)号：KR100771352B1
公开(公告)日：2007-10-29
申请号：KR1020060090642
申请日：2006-09-19
Applicant: 삼성전기주식회사
IPC: H05K3/07
CPC classification number: H05K3/384 , H05K3/0047 , H05K3/0055 , H05K3/06
Abstract: A method of manufacturing a printed circuit board is provided to increase a bonding strength between an insulation layer and a circuit pattern by forming an electrolyte copper plating layer on a conductive carbon material. An electroless copper plating layer(106) is formed on an insulation layer(102). A dry film(108) is applied on the electroless copper plating layer and a circuit pattern is formed by using exposure and developing processes. The electroless copper plating layer, which is exposed from region for a circuit pattern, is removed. A seed layer is formed through a conductive carbon material on the insulation layer from which the electroless copper plating layer is removed. An electrolyte copper plating layer is formed on the conductive carbon material. The dry film is removed and the electroless copper plating layer is removed from the removed portion of the dry film.
Abstract translation: 提供一种制造印刷电路板的方法，通过在导电性碳材料上形成电解质铜电镀层来增加绝缘层和电路图案之间的接合强度。 在绝缘层（102）上形成化学镀铜层（106）。 在无电镀铜层上涂布干膜（108），通过曝光和显影工艺形成电路图案。 从电路图案的区域露出的化学镀铜层被去除。 种子层通过除去化学镀铜层的绝缘层上的导电碳材料形成。 在导电性碳材料上形成电解铜镀层。 除去干膜，并从干膜的去除部分除去无电镀铜层。
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公开(公告)号：KR100952483B1
公开(公告)日：2010-04-13
申请号：KR1020080014405
申请日：2008-02-18
Applicant: 삼성전기주식회사
CPC classification number: H05K3/107 , H05K3/0023 , H05K3/045 , H05K3/423 , H05K3/426 , H05K2201/0376 , H05K2201/09563 , H05K2203/0353 , Y10T29/49126 , Y10T29/49165
Abstract: 인쇄회로기판 및 그 제조방법이 개시된다. 제1 절연재, 제1 절연재에 적층되는 제2 절연재, 제2 절연재에 매립된 회로패턴 및 비아랜드, 제1 절연재를 관통하고 비아랜드와 일체로 형성되며 도전성 물질로 이루어진 비아를 포함하는 인쇄회로기판 및 그 제조방법은, 회로패턴 및 비아랜드가 절연재에 매립되어 있고 회로패턴, 비아랜드 및 비아가 도전성 물질의 형성과정에서 동시에 일체로 형성됨으로써 배선패턴 및 비아의 전기적 신뢰성을 높임과 동시에 비아의 열방출 효과를 높일 수 있고, 회로패턴, 비아랜드 및 비아의 형성과정을 단순화함으로써 기판 제조의 생산성을 높일 수 있다.
인쇄회로기판, 감광성 절연재, 필 도금Abstract translation: 公开了一种印刷电路板及其制造方法。 第一绝缘材料，在所述第一绝缘材料2，绝缘材料，通过电路图案的层压和经由陆地，埋在所述第二绝缘材料和第一绝缘材料与通过由导电材料制成的，电路板的通孔接合区的印刷，其包括一体地形成 及其制造方法，通过土地的电路图案和被嵌入在绝缘材料和电路图案，通过土地和通过所述通孔的同时提高了通过在导电材料的形成过程中一体形成的同时与布线图案的电可靠性和热的 可以提高发射效果，并且可以通过简化电路图案的形成工艺，通过焊盘和通孔来增加衬底制造的生产率。
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公开(公告)号：KR100843367B1
公开(公告)日：2008-07-03
申请号：KR1020070021725
申请日：2007-03-06
Applicant: 삼성전기주식회사
IPC: H05K3/42
CPC classification number: H05K3/421 , H05K3/4038 , H05K2201/09563
Abstract: A printed circuit board and a method for manufacturing the same are provided to realize a fine circuit below a line/space of 10/10 without an additional facility by increasing the degree of freedom for securing a pattern plating thickness. A method for manufacturing a printed circuit board includes the steps of: preparing the printed circuit board having a via hole to conduct between layers; forming a metal seed layer(105) on the printed circuit board including the via hole; forming a first metal plating layer(106) by performing an electrolyte panel plating on the printed circuit board for a via charging at a first static current density and a first inverse current density; etching the metal seed layer and the metal plating layer to make a total thickness of the metal seed layer and the metal plating layer of 0.5 to 2um; forming a second metal plating layer(108) by performing electrolyte pattern plating on the etched printed circuit board for a circuit pattern thickness plating at a second static current density and a second inverse current density; and forming a circuit pattern(109) by removing the first metal plating layer and the metal seed layer of a portion where the second metal plating layer is not formed.
Abstract translation: 提供一种印刷电路板及其制造方法，通过提高确保图案电镀厚度的自由度，通过附加设备实现10/10线以下的精细电路。 一种制造印刷电路板的方法包括以下步骤：制备具有通孔以在层之间传导的印刷电路板; 在包括通孔的印刷电路板上形成金属种子层（105）; 通过在所述印刷电路板上进行电解质板电镀，以第一静态电流密度和第一反向电流密度进行通孔充电来形成第一金属镀层（106）; 蚀刻金属种子层和金属镀层，使金属种子层和金属镀层的总厚度为0.5〜2um; 通过在蚀刻的印刷电路板上以第二静态电流密度和第二反向电流密度进行电路图案厚度镀层的电解质图案电镀，形成第二金属镀层（108）; 以及通过去除不形成第二金属镀层的部分的第一金属镀层和金属种子层来形成电路图案（109）。
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公开(公告)号：KR100738394B1
公开(公告)日：2007-07-12
申请号：KR1020060076593
申请日：2006-08-14
Applicant: 삼성전기주식회사
IPC: H04B1/04
Abstract: A chaos signal generating apparatus and method are provided to solve a problem of the related art that when value of a passive element is changed by a certain degree according to a change in a process, a chaos signal may not be generated at a UWB(Ultra Wide Band) operation frequency. A PN(Pseudo Noise) signal generating unit(51) is configured in a digital logic type and generates a pseudo-random signal in a digital form with a certain frequency. A VCO(Voltage Control Oscillator)(52) generates a clock signal of a certain frequency. A mixer unit(53) mixes the pseudo-random signal with the clock signal to generate a chaos signal and output it. A BPF(Band Pass Filter)(54) filters the chaos signal outputted from the mixer unit(53) so as to become a chaos signal of a desired band and outputs it.
Abstract translation: 提供混沌信号产生设备和方法，以解决相关技术的问题，即当无源元件的值根据处理中的变化而改变一定程度时，混沌信号可能不会在UWB（Ultra 宽带）操作频率。 PN（伪噪声）信号生成单元（51）被配置为数字逻辑类型，并且以具有特定频率的数字形式生成伪随机信号。 VCO（电压控制振荡器）（52）产生一定频率的时钟信号。 混频器单元（53）将伪随机信号与时钟信号混合以生成混沌信号并将其输出。 BPF（带通滤波器）（54）对从混频器单元（53）输出的混沌信号进行滤波，以成为期望频带的混沌信号并将其输出。
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公开(公告)号：KR1020130017371A
公开(公告)日：2013-02-20
申请号：KR1020110079755
申请日：2011-08-10
Applicant: 삼성전기주식회사
CPC classification number: C25D21/02 , C25D17/002
Abstract: PURPOSE: A plating device is provided to increase the temperature of a plating object by indirectly heating the plating object as only a plating solution adjacent to the plating object is heated by a heater. CONSTITUTION: A plating device(100) comprises a plating bath, an anode(130), a cathode(120), and a heater(140). A plating solution is received in the plating bath. The anode is arranged inside the plating bath. The cathode is electrically connected to the plating object arranged inside the plating bath. The heater heats the plating solution adjacent to the plating object.
Abstract translation: 目的：提供电镀装置，通过间接地加热电镀物体来提高电镀物体的温度，因为只有与电镀物体相邻的电镀液被加热器加热。 构成：电镀装置（100）包括电镀槽，阳极（130），阴极（120）和加热器（140）。 在电镀浴中接受镀液。 阳极布置在镀浴内。 阴极与布置在电镀槽内部的电镀物电连接。 加热器加热电镀液附近的电镀液。
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