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公开(公告)号：KR1020020035939A
公开(公告)日：2002-05-16
申请号：KR1020000065763
申请日：2000-11-07
Applicant: 삼성전자주식회사
IPC: H01L23/12
Abstract: PURPOSE: A group-encapsulated half-finished semiconductor chip package is provided to prevent warpage by compensating for the difference of shrinkage ratios caused by an average thermal expansion ratio in upper and lower portions with respect to the thickness center of the semiconductor chip package. CONSTITUTION: A substrate(17) has an upper surface to which a plurality of semiconductor chips(15) are attached. A warpage control pattern(11) is formed in a region between the semiconductor chips of the substrate. An encapsulating part(13) encapsulating the semiconductor chips is formed on the upper surface of the substrate.
Abstract translation: 目的：提供一种组封装的半成品半导体芯片封装，以通过补偿上半部分芯片组件的厚度中心上下部分的平均热膨胀率引起的收缩率差异来防止翘曲。 构成：衬底（17）具有附接有多个半导体芯片（15）的上表面。 翘曲控制图案（11）形成在基板的半导体芯片之间的区域中。 封装半导体芯片的封装部分（13）形成在基板的上表面上。
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公开(公告)号：KR1020160149357A
公开(公告)日：2016-12-28
申请号：KR1020150086003
申请日：2015-06-17
Applicant: 삼성전자주식회사
IPC: H01L25/065 , H01L23/488 , H01L25/07
CPC classification number: H01L25/50 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L25/105 , H01L2224/11849 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13139 , H01L2224/1357 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: 본발명은반도체패키지의제조방법을제공한다. 반도체패키지의제조방법은내부솔더볼을포함하는하부패키지를제공하고, 상기내부솔더볼상에도전성물질을제공하여상기내부솔더볼을감싸는외부솔더볼을형성하고, 상기하부패키지상에상부솔더볼을포함하는상부패키지를제공하고, 제 1 온도에서제 1 공정을수행하여상기상부솔더볼과상기외부솔더볼을결합하고, 그리고, 제 2 온도에서제 2 공정을수행하여상기상부솔더볼, 상기내부솔더볼및 상기외부솔더볼이결합된연결단자를형성하는것을포함한다.
Abstract translation: 提供一种制造半导体封装件的方法。 该方法包括提供具有内部焊球的下部封装，在内部焊球上提供导电材料以形成封装内部焊球的外部焊球，在下部封装上提供具有上部焊球的上部封装，执行 在第一温度下将第一温度连接到外部焊球的第一工艺，以及在第二温度下进行第二工序以将上，内和外焊球团聚到连接端子中。
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公开(公告)号：KR1020090052716A
公开(公告)日：2009-05-26
申请号：KR1020070119345
申请日：2007-11-21
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/4985 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599
Abstract: 본 발명은 반도체 패키지 및 이를 구비한 전자 기기에 관한 것으로, 본 발명의 반도체 패키지는, 반도체 칩과, 상기 반도체 칩을 외부와 전기적으로 연결시키는 외부 단자와, 그리고 상기 반도체 칩이 실장되고 상기 외부 단자가 부착되는, 비평탄면을 갖는 유연성 기판을 포함하는 것을 특징으로 한다. 본 발명에 의하면, 유연성 기판에는 딤플 패턴이 형성되어 있어서 유연성 기판의 하부의 솔더볼 어탯치 부분이 오목하여 솔더 접합 신뢰성이 향상되고 유연성 기판의 상부가 볼록하여 계면 박리 진전이 완화된다.
반도체, 솔더볼, 솔더 접합 신뢰성(SJR), 계면 박리-
公开(公告)号：KR1020080046824A
公开(公告)日：2008-05-28
申请号：KR1020060116325
申请日：2006-11-23
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/00011 , H01L2924/15311 , H01L2924/00014 , H01L2924/00 , H01L2924/01049
Abstract: A semiconductor memory module is provided to protect a semiconductor memory device from physical impact caused by irregularly arranged dummy pads and dummy balls by installing an impact absorption structure on a semiconductor memory package corresponding to dummy pads and dummy balls irregularly arranged in a mother board. A semiconductor memory module includes a mother board(10) and semiconductor memory packages(5). An impact absorption structure(100) is disposed on at least one of the semiconductor memory packages to correspond to dummy pads(24) and dummy balls(28) irregularly arranged on the mother board. The semiconductor memory module can include a DIMM(dual in-line memory module) or an RDIMM(resistor dual in-line memory module). The impact absorption structure can be composed of an impact absorption pattern and a protection housing surrounding the impact absorption pattern wherein a space can be formed between the protection housing and the impact absorption pattern.
Abstract translation: 提供半导体存储器模块以通过在对应于不规则地布置在母板中的虚拟焊盘和虚拟焊盘的半导体存储器封装上安装冲击吸收结构来保护半导体存储器件免受由不规则排列的虚拟焊盘和虚拟焊球引起的物理冲击。 半导体存储器模块包括母板（10）和半导体存储器封装（5）。 冲击吸收结构（100）设置在半导体存储器封装中的至少一个上，以对应于不规则地布置在母板上的虚拟焊盘（24）和虚拟焊球（28）。 半导体存储器模块可以包括DIMM（双列直插存储器模块）或RDIMM（电阻双列直插存储器模块）。 冲击吸收结构可以由冲击吸收图案和围绕冲击吸收图案的保护壳体组成，其中可以在保护壳体和冲击吸收图案之间形成空间。
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公开(公告)号：KR1020170067942A
公开(公告)日：2017-06-19
申请号：KR1020150174320
申请日：2015-12-08
Applicant: 삼성전자주식회사
CPC classification number: H01L25/18 , B23K35/262 , C22C13/00 , H01L21/4853 , H01L23/49811 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/16503 , H01L2224/16507 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2224/75283 , H01L2224/8121 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/8149 , H01L2224/8181 , H01L2224/81815 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/3512 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2924/01028 , H01L2924/01083 , H01L2924/00
Abstract: 3.0 내지 4.0 중량%의은(Ag), 0.75 내지 1.0 중량%의구리(Cu), 0.08 내지 1.0 중량%의니켈(Ni), 및 94 내지 96.17 중량%의주석(Sn)을포함하는솔더조성물을제공할수 있다.
Abstract translation: 本发明涉及一种焊料组合物，其包含3.0至4.0重量％的银（Ag），0.75至1.0重量％的铜（Cu），0.08至1.0重量％的镍（Ni）和94至96.17重量％的锡（Sn） 你可以。
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Patent Agency Ranking
公开(公告)号：KR1020150044515A
公开(公告)日：2015-04-27
申请号：KR1020130123584
申请日：2013-10-16
Applicant: 삼성전자주식회사
CPC classification number: H01L22/12 , G01N23/04 , G21K1/10 , H01L23/3114 , H01L24/48 , H01L25/0657 , H01L2224/48153
Abstract: 엑스레이튜브(X-ray tube) 및상기엑스레이튜브에인접한검출기(detector)가배치된다. 상기엑스레이튜브및 상기검출기사이에시편거치대가배치된다. 상기엑스레이튜브및 상기시편거치대사이에필터(filter)가배치된다. 상기필터(filter)는판상반도체, 입상반도체, 또는이들의조합을갖는다.
Abstract translation: 放置与X射线管相邻的X射线管和检测器。 样品架放置在X射线管和检测器之间。 过滤器放置在X射线管和样品架之间。 滤光器具有板状半导体，粒状半导体或其组合。
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公开(公告)号：KR1020100092775A
公开(公告)日：2010-08-23
申请号：KR1020090012064
申请日：2009-02-13
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01N19/04 , G01N2033/0095
Abstract: PURPOSE: By using the thin film adhesion testing specimen, it exacts and the thin film adhesion testing method using the elastic plate steadily measures the adhesive force between the thin film. Thin films are formed into the optimized form. CONSTITUTION: The wafer having a plurality of substrates(170) divided with the scribe line is prepared. Wafer comprises lower-part facing the upper side and upper side. A plurality of thin films is formed on the upper side of substrate. The thin film comprises the first thin film(178) and the exfoliation object film second thin film(180). The groove(174) having part of depth the blade [blade] is used for the groove forming area included in the lower-part of substrate is formed.
Abstract translation: 目的：通过使用薄膜粘附试验样品，使用弹性板的薄膜粘合试验方法稳定地测量薄膜之间的粘合力。 薄膜形成为优化形式。 构成：准备了划分有划线的多个基板（170）的晶片。 晶片包括面向上侧和上侧的下部。 在基板的上侧形成有多个薄膜。 薄膜包括第一薄膜（178）和剥离对象薄膜第二薄膜（180）。 形成具有叶片[叶片]的一部分深度的槽（174）用于包括在基板的下部中的槽形成区域。
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公开(公告)号：KR100443399B1
公开(公告)日：2004-08-09
申请号：KR1020010065962
申请日：2001-10-25
Applicant: 삼성전자주식회사
IPC: H01L23/36
CPC classification number: H01L23/433 , H01L24/31 , H01L2224/16225 , H01L2224/73253 , H01L2224/73257 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/15312 , H01L2924/15787 , H01L2924/16152 , H01L2924/351 , H01L2924/3512 , H01L2924/00
Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.
Abstract translation: 提供了一种半导体封装及其形成方法。 半导体封装包括具有有源表面和背表面的芯片。 该半导体封装还包括具有上表面和与上表面相对的下表面的衬底。 芯片电连接到基板的上表面。 盖子热耦合到芯片的后表面。 热界面材料（TIM）位于芯片和盖子之间。 TIM包括空隙以减少施加在芯片和TIM上的热机械应力，从而防止封装裂缝。
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公开(公告)号：KR1020030033818A
公开(公告)日：2003-05-01
申请号：KR1020010065962
申请日：2001-10-25
Applicant: 삼성전자주식회사
IPC: H01L23/36
CPC classification number: H01L23/433 , H01L24/31 , H01L2224/16225 , H01L2224/73253 , H01L2224/73257 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/15312 , H01L2924/15787 , H01L2924/16152 , H01L2924/351 , H01L2924/3512 , H01L2924/00
Abstract: PURPOSE: A semiconductor package having thermal interface material(TIM) formed voids is provided to improve the efficiency of heat release by using solder as thermal interface material. CONSTITUTION: A plurality of contact bumps are attached on a lower portion of a CPU(Central Processing Unit) chip. The CPU chip is bonded on an upper surface of a PCB(Printed Circuit Board) by a flip chip bonding method. An outer connection terminal is formed on the lower surface of the PCB, wherein the outer connection terminal is electrically connected with the CPU chip. A cover(140) is located at the upper portion of the CPU chip for releasing the heat from the CPU chip to the outer portion. Thermal interface material(160) is located between the CPU chip and the cover(140) for releasing the heat from the CPU chip to the cover(140). At this time, solder having uniformly distributed voids(180) is used as the thermal interface material(160).
Abstract translation: 目的：提供具有形成空隙的热界面材料（TIM）的半导体封装，以通过使用焊料作为热界面材料来提高散热效率。 构成：在CPU（中央处理单元）芯片的下部附接多个接触凸点。 CPU芯片通过倒装芯片接合方法结合在PCB（印刷电路板）的上表面上。 外部连接端子形成在PCB的下表面上，其中外部连接端子与CPU芯片电连接。 盖子（140）位于CPU芯片的上部，用于将热量从CPU芯片释放到外部。 热界面材料（160）位于CPU芯片和盖（140）之间，用于将热量从CPU芯片释放到盖（140）。 此时，使用具有均匀分布的空隙（180）的焊料作为热界面材料（160）。
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公开(公告)号：KR1020020083743A
公开(公告)日：2002-11-04
申请号：KR1020010023350
申请日：2001-04-30
Applicant: 삼성전자주식회사
IPC: H01L23/36
CPC classification number: H01L25/0652 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01087 , H01L2224/0401
Abstract: PURPOSE: A circuit board having a heating means and multichip package having hermetic sealing part is provided to improve reliability of a solder joint, by preventing a crack on the solder joint and by repairing a previously-generated crack. CONSTITUTION: A plurality of semiconductor chips(26,31) are provided. The circuit board(20) has a mounting surface on which the plurality of semiconductor chips are mounted. A chip mounting part including a land pattern is formed on the mounting surface. A terminal part that electrically connects a conductive interconnection pattern and the semiconductor chip with the exterior is formed in the mounting surface. An electrical connection unit electrically connects the land pattern of the circuit board with the semiconductor chip. A heat emitting unit(30) emits the heat generated from the semiconductor chip to the exterior. A heat interface thermally couples the surface opposite to the mounting surface of the plurality of semiconductor chips to the heat emitting unit. The heat emitting unit surrounds the chip mounting part of the circuit board and the semiconductor chip to form a cavity which is the hermetic sealing part completely isolated from the exterior.
Abstract translation: 目的：提供一种具有加热装置和具有气密密封部分的多芯片封装的电路板，以通过防止焊点上的裂纹和修复先前产生的裂纹来提高焊点的可靠性。 构成：提供多个半导体芯片（26,31）。 电路板（20）具有安装多个半导体芯片的安装面。 在安装面上形成有包括焊盘图案的芯片安装部。 在安装表面上形成有将导电互连图案与半导体芯片电连接到外部的端子部。 电连接单元将电路板的焊盘图案与半导体芯片电连接。 发热单元（30）将从半导体芯片产生的热量发射到外部。 热界面将与多个半导体芯片的安装表面相对的表面热耦合到发热单元。 发热单元围绕电路板的芯片安装部分和半导体芯片，以形成与外部完全隔离的气密密封部分的空腔。
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