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公开(公告)号：KR100766502B1
公开(公告)日：2007-10-15
申请号：KR1020060110611
申请日：2006-11-09
Applicant: 삼성전자주식회사
CPC classification number: H01L23/13 , H01L23/49816 , H01L24/48 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device package is provided to prevent exfoliation between a printed circuit board and a molding material by forming a connecting portion for connecting upper and lower molding materials on the printed circuit board. A semiconductor chip(110) is mounted on an upper surface of a printed circuit board and center-type bonding pads are exposed by a window(121) of the printed circuit board. Bonding wires connect the center-type bonding pads with the printed circuit board through the window. A lower molding material is provided on a lower surface of the printed circuit board to seal the center-type bonding pads and the bonding wires. The semiconductor chip and the upper surface of the printed circuit board are sealed by an upper molding material. The printed circuit board has a connecting portion(126) connecting the upper and lower molding materials.
Abstract translation: 提供半导体器件封装，通过形成用于连接印刷电路板上的上下成型材料的连接部分来防止印刷电路板和成型材料之间的剥离。 半导体芯片（110）安装在印刷电路板的上表面上，并且中心型接合焊盘通过印刷电路板的窗（121）露出。 接合线通过窗口将中心型接合焊盘与印刷电路板连接。 在印刷电路板的下表面上设置下部成型材料，以密封中心型接合焊盘和接合线。 半导体芯片和印刷电路板的上表面被上模塑材料密封。 印刷电路板具有连接上下成型材料的连接部分（126）。
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公开(公告)号：KR101585211B1
公开(公告)日：2016-01-13
申请号：KR1020090030906
申请日：2009-04-09
Applicant: 삼성전자주식회사
IPC: H01L23/488
CPC classification number: H05K1/111 , H05K3/3436 , H05K3/368 , H05K2201/09381 , H05K2201/09418 , H05K2201/09427 , Y02P70/611 , Y02P70/613
Abstract: 전자장치를제공한다. 이전자장치는제1 면을갖는제1 구조체를포함한다. 상기제1 면에제1 랜드영역이제공된다. 상기제1 랜드영역은상기제1 면에서장축및 단축을갖는다. 상기제1 면과마주보는제2 면을갖는제2 구조체가제공된다. 상기제2 면에제2 랜드영역이제공된다. 상기제2 랜드영역은상기제2 면에서장축및 단축을갖는다. 상기제1 및제2 구조체들사이에개재되며, 상기제1 및제2 랜드영역들과전기적으로연결된연결구조체가제공된다. 상기제1 및제2 랜드영역들의장축들은서로다른방향성을갖는다.
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公开(公告)号：KR101534682B1
公开(公告)日：2015-07-08
申请号：KR1020090021719
申请日：2009-03-13
Applicant: 삼성전자주식회사
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L24/13 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02126 , H01L2224/0401 , H01L2224/05558 , H01L2224/05571 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1132 , H01L2224/1134 , H01L2224/11464 , H01L2224/13006 , H01L2224/13018 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012
Abstract: 솔더범프에의하여반도체장치와 PCB 기판이접합되는플립칩본딩용반도체장치에있어서, 열적불일치(thermal mismatch)로인하여발생되는외력을솔더범프가흡수하고이를각 부분에골고루분산시켜야함에도, 솔더범프에국부적인스트레스가집중되면서발생되는신뢰성문제를개선한다. 이를위하여, 본딩패드와솔더범프가연결되도록솔더랜드의중심에서패시베이션막, 완충막, 절연막이제거되는제1리세스부가형성되고, 제1리세스부의주변에는스틱을구성하도록소정거리를두고절연막이제거되는제2리세스부가더 형성된다. 따라서, 스틱이지팡이처럼완충막에지지됨으로써, 솔더범프는외력에의하여일측에서들뜨거나타측에서눌리지않게된다. 특히, 반도체장치가고집적화되고, 솔더랜드의사이즈가대폭감축됨에따라, 제1리세스부는장축과단축을가지는블럭형태로구성되고, 제2리세스부는제1리세스부의장축의연장선과만나지않도록한 쌍의블럭형태로구성되되, 한쌍의제2리세스부의중심을잇는직선은외력의방향과일치하도록한다.
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公开(公告)号：KR1020100112405A
公开(公告)日：2010-10-19
申请号：KR1020090030906
申请日：2009-04-09
Applicant: 삼성전자주식회사
IPC: H01L23/488
CPC classification number: H05K1/111 , H05K3/3436 , H05K3/368 , H05K2201/09381 , H05K2201/09418 , H05K2201/09427 , Y02P70/611 , Y02P70/613
Abstract: PURPOSE: An electronic apparatus is provided to effectively disperse stresses applied to connection structures by varying the widths of the connection structures. CONSTITUTION: A first structure(C3) with a first side is prepared. A first land area(CRR1) includes a longitudinal axis and a short axis on the first side of the first structure. A second structure(B3) includes a second side to be opposite with the first side. A secondary land area(CRR2) includes a longitudinal axis and a short axis on the second side of the second structure. Connection structures are interposed between the first structure and the second structure. Connection structures are electrically connected to the first and the secondary land areas.
Abstract translation: 目的：提供一种电子设备，通过改变连接结构的宽度来有效地分散施加到连接结构上的应力。 构成：准备具有第一面的第一结构（C3）。 第一陆地区域（CRR1）包括在第一结构的第一侧上的纵向轴线和短轴线。 第二结构（B3）包括与第一侧相对的第二侧。 第二结构区域（CRR2）包括在第二结构的第二侧上的纵轴和短轴。 连接结构插入在第一结构和第二结构之间。 连接结构电连接到第一和第二陆地区域。
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公开(公告)号：KR1020040075629A
公开(公告)日：2004-08-30
申请号：KR1020030011209
申请日：2003-02-22
Applicant: 삼성전자주식회사
CPC classification number: H01L25/0657 , H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2225/06582 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
Abstract: PURPOSE: A multi-chip package with reduced chip crack and a fabricating method thereof are provided to prevent the chip crack by reducing the constraining force of a sealing resin to the chip. CONSTITUTION: A plurality of semiconductor chips(130,140) are stacked on an upper surface of a substrate(110) by using an adhesive. The resultant structure is sealed up by using a sealing resin(150). A soft element(155a) is formed on an interface between the semiconductor chips and the sealing resin. The soft element is more flexible than the sealing resin. The soft element is formed on one side of the semiconductor chip selected from the semiconductor chips.
Abstract translation: 目的：提供减少芯片裂纹的多芯片封装及其制造方法，以通过减小密封树脂对芯片的约束力来防止芯片裂纹。 构成：通过使用粘合剂将多个半导体芯片（130,140）堆叠在基板（110）的上表面上。 所得结构通过使用密封树脂（150）密封。 在半导体芯片和密封树脂之间的界面上形成软元件（155a）。 软元件比密封树脂更灵活。 软元件形成在从半导体芯片中选择的半导体芯片的一侧上。
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Patent Agency Ranking
公开(公告)号：KR1020030024533A
公开(公告)日：2003-03-26
申请号：KR1020010061438
申请日：2001-10-05
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/10 , B23K1/0008 , B23K35/0222 , B23K35/0244 , B23K2201/40 , H01L24/13 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13011 , H01L2224/13099 , H01L2224/81801 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/351 , H05K1/111 , H05K3/3436 , H05K2201/09381 , H05K2201/0969 , H05K2201/10257 , H05K2203/0465 , Y02P70/611 , Y02P70/613 , Y10T428/12014 , Y10T428/12222 , H01L2224/29099 , H01L2924/00
Abstract: PURPOSE: A reliable solder structure having a cavity and a method for fabricating the same are provided to improve the reliability of contact between a chip and a printed circuit board by forming a cavity on a solder structure. CONSTITUTION: A barrel-shaped solder structure(26) has a center cavity(28). The first seeding point is formed on a ring-shaped center portion having non-conductivity and non-wetting by forming an annular conductive pad(30) instead of a circular conductive pad on an upper plane element(14). The first internal cavity is formed by surface tension and viscosity of a melted solder. An internal cavity(28) is formed since a lower plane element(18) includes a ring-shaped conductive pad(32) and the second seeding point. A plurality of holes(34,36) are formed on the annular conductive pad(30) and the ring-shaped conductive pad(32), respectively.
Abstract translation: 目的：提供具有空腔的可靠的焊料结构及其制造方法，以通过在焊料结构上形成空腔来提高芯片与印刷电路板之间的接触的可靠性。 构成：桶形焊料结构（26）具有中心腔（28）。 第一种子点通过在上平面元件（14）上形成环形导电垫（30）代替圆形导电垫而形成在具有非导电性和不润湿性的环形中心部分上。 第一内腔由熔融焊料的表面张力和粘度形成。 形成内腔（28），因为下平面元件（18）包括环形导电垫（32）和第二接种点。 多个孔（34,36）分别形成在环形导电垫（30）和环形导电垫（32）上。
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公开(公告)号：KR1020090013564A
公开(公告)日：2009-02-05
申请号：KR1020070077808
申请日：2007-08-02
Applicant: 삼성전자주식회사
IPC: H01L23/495
CPC classification number: H05K3/3426 , H01L23/49548 , H01L23/49555 , H01L23/49575 , H01L23/49582 , H01L24/48 , H01L25/105 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1532 , H01L2924/181 , H05K2201/10477 , H05K2201/10689 , Y02P70/613 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package device and manufacturing method thereof are provided to improve the reliability of the electrical contact of junction under the thermal cycle ring environment according to the operation of the semiconductor chip by forming the exposed lead frame package. The semiconductor package device(10) comprises the semiconductor chip(2) protected by the packout section(1) and the substrate(3), the semiconductor chip, the mount and lead(7) and the joining material(8). The front end part(4) of the lead is electrically connected to the semiconductor chip, the back end is extended to the substrate. The joining material be electrically connected between the junction of the lead and the substrate. The bonding material is solder, gold, copper, silver, other including aluminum etc. The packout section surrounds one side of the semiconductor chip and the wire.
Abstract translation: 提供一种半导体封装器件及其制造方法，通过形成暴露的引线框封装，根据半导体芯片的工作，提高热循环环路下的接点的电接触的可靠性。 半导体封装器件（10）包括被封装部分（1）和衬底（3），半导体芯片，安装件和引线（7）和接合材料（8）保护的半导体芯片（2）。 引线的前端部分（4）与半导体芯片电连接，后端延伸到基板。 接合材料电连接在引线和基板的接合处之间。 接合材料是焊料，金，铜，银，其它包括铝等。封装部分围绕半导体芯片和电线的一侧。
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公开(公告)号：KR1020070027190A
公开(公告)日：2007-03-09
申请号：KR1020050082558
申请日：2005-09-06
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/4824 , H01L2924/15311
Abstract: A stack package having a spacer substrate is provided to secure a gap between a semiconductor chip and a resin encapsulation and to prevent mechanical stress therebetween by using an opening unit formed on the spacer substrate. A window is lengthily formed on a center of a wiring substrate(120). A semiconductor chip(130) is adhered to an upper surface(121) of the wire substrate to expose center pads through the window. A bonding wire electrically connects the center pads to the wire substrate through the window. A resin encapsulation(150) encapsulates a center of a lower surface(123) of the wire substrate to protect the center pads exposed through the window and the bonding wire. Plural boards on chip package(110) have a solder ball(160) formed on the lower surface of the wire substrate at an outer side of the resin encapsulation. A substrate body(171) is disposed between the board on chip packages. An opening unit is formed on a center of the substrate body to be opposite to an upper package. A spacer substrate is formed on a lower surface of the substrate body corresponding to the solder ball to be connected to the wire substrate of a lower package. The spacer substrate has plural connecting balls(173).
Abstract translation: 提供具有间隔基板的堆叠封装，以确保半导体芯片和树脂封装之间的间隙，并且通过使用形成在间隔基板上的开口单元来防止它们之间的机械应力。 在布线基板（120）的中心上形成有窗口。 半导体芯片（130）被粘附到线基板的上表面（121），以通过窗口露出中心焊盘。 接合线通过窗口将中心焊盘电连接到线基底。 树脂封装（150）封装线基板的下表面（123）的中心，以保护通过窗口和接合线暴露的中心焊盘。 多个片上封装（110）具有在树脂封装的外侧形成在线基板的下表面上的焊球（160）。 衬底主体（171）设置在片上芯片封装之间。 开口单元形成在与上包装件相对的基板主体的中心。 间隔基板形成在与焊料球相对应的基板主体的下表面上，以连接到下封装的导线基板。 间隔基板具有多个连接球（173）。
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公开(公告)号：KR100524948B1
公开(公告)日：2005-11-01
申请号：KR1020030011209
申请日：2003-02-22
Applicant: 삼성전자주식회사
CPC classification number: H01L25/0657 , H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2225/06582 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
Abstract: 종래의 멀티 칩 패키지에서는 칩 적층을 위하여 사용한 접착제에 의하여 냉각시 칩 두께 방향으로 변형력이 작용하나, 칩 주위를 감싸고 있는 봉합수지가 칩을 강하게 구속함에 따라 응력 집중으로 칩 크랙이 발생하는 문제가 있다. 본 발명은 이를 개선하고자, 칩의 주위(예를 들어, 칩의 측면 또는 상면)에 봉합수지보다 유연한 완충재(soft element)를 구비하여 칩의 두께 방향 운동성을 확보함으로써 응력 집중을 억제하여 칩 크랙을 방지하는 것이다.
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