公开(公告)号：KR1020080112878A

公开(公告)日：2008-12-26

申请号：KR1020070061876

申请日：2007-06-22

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  박배호 ,  박영수 ,  서순애 ,  김진수

IPC: H01L27/115 ,  H01L21/8247 ,  B82Y10/00

CPC classification number: G11C13/0004 ,  B82Y10/00 ,  H01L21/02252

Abstract: A resistivity memory device and a manufacturing method thereof are provided to improve the degree of integration of a memory device by limiting a resistance conversion layer of a nanorods structure included in a unit memory structure. A resistivity memory device comprises a middle electrode(42), a memory structure(43) and an upper electrode(44). The middle electrode comprises an overhanging construction formed on a switch(41). The memory structure is formed on the middle electrode. The memory structure comprises a resistance conversion layer(43a) and an insulating layer(43b). A resistance conversion layer is formed with a nanorods structure. The insulating layer is formed in the side of the resistance conversion layer. The upper electrode is formed on the memory structure.

Abstract translation: 提供了一种电阻率存储器件及其制造方法，通过限制单元存储器结构中包括的纳米棒结构的电阻转换层来提高存储器件的集成度。 电阻率存储器件包括中间电极（42），存储结构（43）和上电极（44）。 中间电极包括形成在开关（41）上的突出结构。 存储器结构形成在中间电极上。 存储器结构包括电阻转换层（43a）和绝缘层（43b）。 形成具有纳米棒结构的电阻转换层。 绝缘层形成在电阻转换层的侧面。 上部电极形成在存储器结构上。

公开(公告)号：KR1020080112609A

公开(公告)日：2008-12-26

申请号：KR1020070061207

申请日：2007-06-21

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  김동욱 ,  박영수 ,  서순애 ,  박배호 ,  강보수 ,  안승언 ,  이창범

IPC: H01L27/115 ,  B82Y40/00

CPC classification number: G11C13/0004 ,  B82Y10/00

Abstract: A resistivity memory device and manufacturing method thereof are provided to control the location and form of an overhanging construction selectively and arbitrarily by providing various manufacturing methods of the overhanging construction formed in a middle electrode. A resistivity memory device comprises a middle electrode(32), a resistance conversion layer(33) and an upper electrode(34). The middle electrode is formed on a switch(31). The middle electrode is composed of a overhanging construction(p). The resistance conversion layer is formed on the middle electrode. The upper electrode is formed on the resistance conversion layer.

Abstract translation: 提供一种电阻率记忆装置及其制造方法，通过提供形成在中间电极中的突出结构的各种制造方法，有选择地和任意地控制悬垂结构的位置和形状。 电阻率存储器件包括中间电极（32），电阻转换层（33）和上电极（34）。 中间电极形成在开关（31）上。 中间电极由突出构造（p）组成。 电阻转换层形成在中间电极上。 上电极形成在电阻转换层上。

公开(公告)号：KR1020090014007A

公开(公告)日：2009-02-06

申请号：KR1020070078209

申请日：2007-08-03

Applicant: 삼성전자주식회사

Inventor： 김동철 ,  정란주 ,  서순애 ,  박배호 ,  이장원 ,  정현종 ,  김진수

IPC: H01L29/872

CPC classification number: H01L29/872 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/24 ,  H01L29/47

Abstract: A schottky diode and memory device comprising the same is provided to realize a schottky diode with a PN diode or MOSFET by using contact of Nb oxide layer and metal layer. A schottky diode includes a first metal layer(10) and a Nb oxide layer(20). A Nb oxide layer is formed on the first metal layer, and the second metal layer(30) is formed on the Nb oxide layer. A memory device comprises a storage node and the switching element connected to the storage node. The storage node includes a data storage layer which is composed of resistance change layer, phase change layer, ferroelectric layer or magnetic layer.

Abstract translation: 提供肖特基二极管和包含该肖特基二极管的存储器件以通过使用Nb氧化物层和金属层的接触来实现具有PN二极管或MOSFET的肖特基二极管。 肖特基二极管包括第一金属层（10）和Nb氧化物层（20）。 在第一金属层上形成Nb氧化物层，在Nb氧化物层上形成第二金属层（30）。 存储设备包括存储节点和连接到存储节点的交换元件。 存储节点包括由电阻变化层，相变层，铁电层或磁性层构成的数据存储层。