公开(公告)号：KR101334177B1

公开(公告)日：2013-11-28

申请号：KR1020070016033

申请日：2007-02-15

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 정지심 ,  류명관 ,  권장연 ,  박경배 ,  한민구 ,  이상윤 ,  박중현 ,  한상면 ,  김선재

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L29/42384 ,  H01L2029/7863

Abstract: 본 발명은 박막 트랜지스터 및 그 제조 방법에 관한 것이다. 하부 구조체; 상기 하부 구조체 상에 다수의 도핑 영역을 포함하여 형성된 반도체층; 상기 반도체층 상에 형성된 이격되어 형성된 제 1절연층 및 제 2절연층; 상기 제 1절연층 및 상기 제 2절연층 상에 형성된 제 3절연층; 및 상기 제 3절연층의 상기 제 1절연층 및 상기 제 2절연층에 대응되는 영역 사이에 형성된 게이트 전극층;을 포함하는 박막 트랜지스터를 제공한다.

公开(公告)号：KR1020080076292A

公开(公告)日：2008-08-20

申请号：KR1020070016033

申请日：2007-02-15

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 정지심 ,  류명관 ,  권장연 ,  박경배 ,  한민구 ,  이상윤 ,  박중현 ,  한상면 ,  김선재

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L29/42384 ,  H01L2029/7863 ,  H01L29/78675

Abstract: A thin film transistor and a manufacturing method thereof are provided to change doping level for respective semiconductor layer regions by adjusting thickness and location of first, second, and third insulation layers. A thin film transistor comprises a lower structure(11), a semiconductor layer(12), first and second insulation layers(14a,14b), and a third insulation layer(16), and a gate electrode layer(17). The semiconductor layer includes a plurality of doped regions(12b,12c,12d) on the lower structure. The first and second insulation layers are formed on the semiconductor layer, separated from each other. The third insulation layer is formed on the first and second insulation layers. The gate electrode layer is formed on the third insulation layer between the first and second insulation layers. The width of the third insulation layer is longer than that between the first and second insulation layers and shorter than that between the left part of the first insulation layer and the right part of the second insulation layer.

Abstract translation: 提供薄膜晶体管及其制造方法，通过调整第一，第二和第三绝缘层的厚度和位置来改变各半导体层区域的掺杂水平。 薄膜晶体管包括下部结构（11），半导体层（12），第一和第二绝缘层（14a，14b）以及第三绝缘层（16）和栅电极层（17）。 半导体层包括在下部结构上的多个掺杂区域（12b，12c，12d）。 第一绝缘层和第二绝缘层形成在半导体层上，彼此分离。 第三绝缘层形成在第一和第二绝缘层上。 栅电极层形成在第一和第二绝缘层之间的第三绝缘层上。 第三绝缘层的宽度比第一绝缘层和第二绝缘层之间的宽度长，并且比第一绝缘层的左部分和第二绝缘层的右部分之间的宽度短。

公开(公告)号：KR1020070115276A

公开(公告)日：2007-12-06

申请号：KR1020060049474

申请日：2006-06-01

Applicant: 삼성전자주식회사

Inventor： 박중현 ,  이경민 ,  이지윤

IPC: H01L21/02

CPC classification number: H01L21/68707 ,  H01L21/67742 ,  H01L21/68728

Abstract: An apparatus for manufacturing a semiconductor is provided to prevent wafer damage and generation of particles by using a curved-shape guide. An ion implantation process is performed on a process chamber(150). An electrostatic chuck platen(140) vertically loads a wafer that is treated in the process chamber. A load lock stores plural wafers. A wafer transfer robot transfers the wafer between the electrostatic chuck and the load lock. A curved-shape guide(160) is arranged in the proximity of the electrostatic chuck to receive a dropping wafer released from the electrostatic chuck. The guide includes a first part, a second part, and a third part. The first part is extended downwardly. The second part is separated from the first part to be contacted to the surface of the dropping wafer from the electrostatic chuck. The second part is extended upwardly. The third unit connects to the first and the second parts and has a curvature contacting to an edge of the wafer.

Abstract translation: 提供一种用于制造半导体的装置，以通过使用弯曲形状的引导件来防止晶片损坏和产生颗粒。 在处理室（150）上执行离子注入工艺。 静电卡盘台板（140）垂直地加载在处理室中处理的晶片。 负载锁存储多个晶片。 晶片传送机器人在静电卡盘和装载锁之间传送晶片。 在静电吸盘附近设置弯曲形状的引导件160，以接收从静电卡盘释放的下落晶片。 引导件包括第一部分，第二部分和第三部分。 第一部分向下延伸。 第二部分与第一部分分离，以从静电卡盘与滴下晶片的表面接触。 第二部分向上延伸。 第三单元连接到第一和第二部分，并且具有与晶片的边缘接触的曲率。