公开(公告)号：KR101762661B1

公开(公告)日：2017-08-04

申请号：KR1020100091504

申请日：2010-09-17

Applicant: 삼성전자주식회사

Inventor： 김태현 ,  김경현 ,  심재황 ,  신재진 ,  임종흔 ,  박현민

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

Abstract: 에어갭(air gap)을갖는반도체소자제조방법이개시되어있다. 기판상에서로이격된복수개의예비게이트구조물들의측벽및 예비게이트구조물들사이의기판상면에캐핑막패턴을형성하고, 예비게이트구조물들의상면및 캐핑막패턴의상면상에차단막을형성한다. 차단막및 캐핑막패턴일부를제거하여예비게이트구조물들의측벽일부에캐핑막패턴을형성한다. 캐핑막패턴에의해커버되지않은예비게이트구조물들부분상에도전막을형성하고, 예비게이트구조물들과반응시켜게이트구조물들을형성한다. 게이트구조물들사이에에어갭을갖는제2 절연막을기판상에형성한다. 에어갭 형성에의해, 기생커패시턴스를감소시킬수 있고, 에어갭도충분히크고균일하게형성될수 있다.

公开(公告)号：KR1020120030173A

公开(公告)日：2012-03-28

申请号：KR1020100091504

申请日：2010-09-17

Applicant: 삼성전자주식회사

Inventor： 김태현 ,  김경현 ,  심재황 ,  신재진 ,  임종흔 ,  박현민

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573 ,  H01L21/02362 ,  H01L21/265

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce parasitic capacitance by forming an insulation layer with an air gap between gate structures. CONSTITUTION: A capping layer is formed on a part of a sidewall of a preliminary gate structure. A conductive layer is formed on a part of preliminary gate structures which are not covered with a capping film pattern. Gate structures(242,244,246,248) are formed by reacting the conductive layer with the preliminary gate structures. A second insulation layer(260) is formed on the substrate between the gate structures. The second insulation layer has an air gap.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，通过在栅极结构之间形成具有气隙的绝缘层来减小寄生电容。 构成：在预选栅极结构的侧壁的一部分上形成覆盖层。 导电层形成在未被封盖膜图案覆盖的预选栅极结构的一部分上。 栅极结构（242,244,246,248）通过使导电层与预选栅极结构反应而形成。 在栅极结构之间的衬底上形成第二绝缘层（260）。 第二绝缘层具有气隙。

公开(公告)号：KR1020080073035A

公开(公告)日：2008-08-08

申请号：KR1020070011532

申请日：2007-02-05

Applicant: 삼성전자주식회사

Inventor： 이종수 ,  김태원 ,  황인석 ,  박기종 ,  김광복 ,  박세정 ,  조성민 ,  배진우 ,  박현민

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053

Abstract: A method of filling a trench is provided to completely remove a remaining material from a mask pattern by filling a trench using an oxide material and removing an upper portion of the oxide material using an etching gas. A mask pattern(106) is formed on a substrate(100). A trench(108) is formed in the substrate by etching the substrate using the mask pattern. A first oxide film is formed on the mask pattern, such that the trench is buried. A CMP(Chemical Mechanical Polishing) is performed on the first oxide film, until a portion of the mask pattern is exposed. An upper portion of the first oxide film is removed by using a process gas having a predetermined etching selection ratio between a silicon nitride material and a silicon oxide material, and a recess(112) is formed to expose a portion of a side portion of the mask pattern. A second oxide film is formed on the mask pattern, such that the recess is buried.

Abstract translation: 提供一种填充沟槽的方法，通过使用氧化物材料填充沟槽并使用蚀刻气体去除氧化物材料的上部，从掩模图案中完全除去剩余的材料。 掩模图案（106）形成在基板（100）上。 通过使用掩模图案蚀刻衬底，在衬底中形成沟槽（108）。 在掩模图案上形成第一氧化物膜，使得沟槽被埋置。 在第一氧化物膜上进行CMP（化学机械抛光），直到掩模图案的一部分露出。 通过使用在氮化硅材料和氧化硅材料之间具有预定蚀刻选择比的处理气体来除去第一氧化物膜的上部，并且形成凹部（112）以暴露出部分 掩模图案。 在掩模图案上形成第二氧化膜，使得凹部被埋入。