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公开(公告)号：KR1020140112672A
公开(公告)日：2014-09-24
申请号：KR1020130027017
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/15 , H01L21/8247 , H01L27/115
CPC classification number: H01L27/228 , G11C11/161 , H01L43/12 , G11C11/15 , H01L27/222 , H01L43/08
Abstract: In a method for manufacturing a magnetoresistive memory device, first and second patterns are extended in a first direction and are alternately arranged in a second direction which is vertical to the first direction. The first and second patterns are formed on a substrate. First opening parts extended in the first direction are formed by removing a part of the second patterns. A source line filling each first opening part is formed. Third opening parts are formed by removing parts of the second patterns exposed by second opening parts using a mask with the second opening parts which are extended in the second direction and are formed along the first direction. Third patterns filling the third opening parts are formed. Fourth opening parts are formed by removing the second patterns surrounded by the first and third patterns. A contact plug filling each fourth opening part is formed.
Abstract translation: 在制造磁阻存储器件的方法中，第一和第二图案沿第一方向延伸并且沿与第一方向垂直的第二方向交替布置。 第一和第二图案形成在基板上。 通过去除一部分第二图案形成沿第一方向延伸的第一开口部分。 形成填充每个第一开口部的源极线。 通过使用具有第二开口部的掩模除去由第二开口部暴露的第二图案的部分，形成第三开口部，该第二开口部沿第二方向延伸并且沿第一方向形成。 形成填充第三开口部的第三图案。 通过去除由第一和第三图案包围的第二图案形成第四开口部分。 形成填充每个第四开口部的接触塞。
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公开(公告)号：KR1020150124533A
公开(公告)日：2015-11-06
申请号：KR1020140050867
申请日：2014-04-28
Applicant: 삼성전자주식회사
IPC: H01L21/764 , H01L21/027 , H01L21/20
CPC classification number: H01L43/12 , H01L27/228 , H01L43/08
Abstract: 반도체소자의제조방법이제공된다. 기판상에도전필라들이형성되고, 상기도전필라들의사이에차례로희생층및 몰딩구조체가형성된다. 상기몰딩구조체상에상기도전필라들과연결되는도전층이형성되고상기희생층을제거하여에어갭이형성된다. 상기몰딩구조체를제거하여연장된에어갭이형성되고상기도전층을패터닝하여상기연장된에어갭이노출된다.
Abstract translation: 本发明提供一种制造半导体器件的方法。 导电柱形成在基板上，并且在导电柱之间依次形成牺牲层和模制结构。 连接到导电柱的导电层形成在模制结构上，消除牺牲层以形成气隙。 消除模制结构以形成膨胀的空气间隙，并且将导电层图案化以暴露膨胀的气隙。
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公开(公告)号：KR1020140112682A
公开(公告)日：2014-09-24
申请号：KR1020130027037
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/15 , H01L21/8247 , H01L27/115
CPC classification number: H01L43/12 , G11C11/161 , H01L27/228 , H01L43/08 , G11C11/15 , H01L27/222
Abstract: A manufacturing method for a magnetoresistive memory device includes a step of forming first and second patterns which are alternately and repeatedly arranged to be in contact with each other on a substrate. A first capping film is formed on the upper surface of the first and second patterns. A first opening is formed by removing a part of the first capping layer and the second pattern below the capping layer to expose the upper surface of the substrate. A source line filling the lower part of the first opening is formed. A second capping film pattern filling the upper part of the first opening is formed. A second opening is formed by removing a part of the first capping film and the second pattern below the part of the first capping film. A contact plug and a pad layer which are sequentially stacked on the substrate while filling the second opening are formed to be integrated together.
Abstract translation: 一种用于磁阻存储器件的制造方法包括形成交替重复地布置成在衬底上彼此接触的第一和第二图案的步骤。 在第一和第二图案的上表面上形成第一覆盖膜。 通过去除覆盖层下方的第一覆盖层和第二图案的一部分以暴露衬底的上表面而形成第一开口。 形成填充第一开口的下部的源极线。 形成填充第一开口的上部的第二封盖膜图案。 通过将第一封盖膜的一部分和第二图案移除到第一封盖膜的部分下方而形成第二开口。 在填充第二开口时顺序堆叠在基板上的接触塞和垫层形成为一体化。
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公开(公告)号：KR101916223B1
公开(公告)日：2018-11-07
申请号：KR1020120038710
申请日：2012-04-13
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/66666 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/42332 , H01L29/7827
Abstract: 반도체장치가제공된다. 상기반도체장치는, 기판상에서수직방향으로연장하며, 질소가도핑된반도체층을포함하는채널영역; 상기채널영역의일 측벽상에서수직방향으로이격되어배치되는복수개의게이트전극들; 및상기채널영역및 상기게이트전극들사이의게이트유전막을포함한다.
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Patent Agency Ranking
公开(公告)号：KR1020140011872A
公开(公告)日：2014-01-29
申请号：KR1020120079541
申请日：2012-07-20
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L21/823885
Abstract: In a method for manufacturing a vertical memory device, sacrificial layers and insulating layers are formed on a substrate. The sacrificial layers and the insulating layers are partially etched to form an opening part for exposing the surface of a substrate. A charge trapping layer and a tunnel insulating layer are formed in the sidewall of the opening part. A channel layer including N-type-impurity-doped polysilicon is formed along the inner wall profile of the opening part on the tunnel insulating layer. A burying insulating pattern is formed at the opening part formed in the channel layer. Also, a blocking dielectric layer and a control gate are formed on the charge trapping layer of one sidewall of the channel layer.
Abstract translation: 在垂直存储器件的制造方法中，在衬底上形成牺牲层和绝缘层。 牺牲层和绝缘层被部分蚀刻以形成用于暴露衬底表面的开口部分。 电荷捕获层和隧道绝缘层形成在开口部分的侧壁中。 沿着隧道绝缘层上的开口部分的内壁轮廓形成包括N型杂质掺杂多晶硅的沟道层。 在形成于通道层中的开口部分形成埋入绝缘图案。 此外，在沟道层的一个侧壁的电荷捕获层上形成阻挡介质层和控制栅极。
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公开(公告)号：KR102101407B1
公开(公告)日：2020-04-16
申请号：KR1020130027017
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/15 , H01L21/8247 , H01L27/115
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公开(公告)号：KR101713871B1
公开(公告)日：2017-03-09
申请号：KR1020130027037
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/15 , H01L21/8247 , H01L27/115
CPC classification number: H01L43/12 , G11C11/161 , H01L27/228
Abstract: 자기저항메모리장치제조방법에서, 기판상에서로접촉하여교대로반복적으로배치된제1 및제2 패턴들을형성한다.제1 및제2 패턴들상면에제1 캐핑막을형성한다. 제1 캐핑막의일부및 그아래의제2 패턴을제거하여기판상면을노출시키는제1 개구를형성한다. 제1 개구의하부를채우는소스라인을형성한다. 제1 개구의상부를채우는제2 캐핑막패턴을형성한다. 제1 캐핑막의일부및 그아래의제2 패턴을제거하여제2 개구를형성한다. 제2 개구를채우며기판상에순차적으로적층된콘택플러그및 패드막을일체적으로형성한다.
Abstract translation: 制造磁阻随机存取存储器（MRAM）器件的方法包括以交替和重复的布置在衬底上形成第一和第二图案，在第一和第二图案的顶表面上形成第一封盖层，以及去除第一和第二图案的第一部分 盖层和其下的第二图案的一部分以形成暴露基板的第一开口。 所述方法还包括分别形成填充所述第一开口的下部的源极线，分别形成填充所述第一开口的上部的第二封盖层图案，以及移除所述第一封盖层的第二部分及其下面的第二图案的一部分， 形成露出衬底的第二开口。 然后，将接触塞和垫层一体地形成并依次堆叠在基板上以填充第二开口。
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公开(公告)号：KR1020130116116A
公开(公告)日：2013-10-23
申请号：KR1020120038710
申请日：2012-04-13
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/66666 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/42332 , H01L29/7827 , H01L29/7926
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve electrical characteristics by forming a channel region including a polysilicon layer. CONSTITUTION: A channel region (120) is extended on a substrate in the vertical direction. The channel region includes a semiconductor layer. The semiconductor layer includes nitrogen. Gate electrodes (150) are separated from each other on the sidewall of the channel region in the vertical direction. A gate dielectric layer (140) is formed in the channel region and between the gate electrodes.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过形成包括多晶硅层的沟道区来改善电特性。 构成：通道区域（120）在垂直方向上在基板上延伸。 沟道区域包括半导体层。 半导体层包括氮。 栅电极（150）在垂直方向上在沟道区域的侧壁上彼此分离。 栅极电介质层（140）形成在沟道区域和栅电极之间。
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公开(公告)号：KR1020120123885A
公开(公告)日：2012-11-12
申请号：KR1020110041493
申请日：2011-05-02
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A storage device including an authentication device and an authentication device connection means are provided to prevent an illegal copy of contents stored in the storage device which an authentication function is not equipped. CONSTITUTION: A storage unit(306) stores authentication device identifying information. An interface unit(302) is connected to a host device(100) through a first interface. An authentication processing unit(304) receives an authentication request signal requesting authentication of a storage device connected to the host device through the interface unit from the host device and outputs an authentication response signal to the host device through the interface unit. The authentication response signal includes data about a performing result of an authentication process referring to the authentication device identifying information. [Reference numerals] (100) Host device; (110) Authentication device identifying module; (200) Storage unit; (210) Large capacity storage unit; (220) Memory unit; (230) Bridge controller; (240) Second interface; (250) Third interface; (260) Fourth interface; (300) Authentication device; (302) Interface unit; (304) Authentication processing unit; (306) Storage unit; (310) First interface
Abstract translation: 目的：提供一种包括认证装置和认证装置连接装置的存储装置，以防止存储在不具备认证功能的存储装置中的内容的非法复制。 构成：存储单元（306）存储认证设备识别信息。 接口单元（302）通过第一接口连接到主机设备（100）。 认证处理单元（304）通过接口单元从主机装置接收请求认证与主装置连接的存储装置的认证请求信号，并通过接口单元向主装置输出认证响应信号。 认证响应信号包括关于认证设备识别信息的认证处理的执行结果的数据。 （附图标记）（100）主机设备; （110）认证设备识别模块; （200）存储单元; （210）大容量存储单元; （220）存储单元; （230）桥控制器; （240）第二界面; （250）第三界面; （260）第四界面; （300）验证设备; （302）接口单元; （304）认证处理单元; （306）存储单元; （310）第一界面
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