-
公开(公告)号：KR1020080061719A
公开(公告)日：2008-07-03
申请号：KR1020060136734
申请日：2006-12-28
Applicant: 삼성전자주식회사
IPC: H01G4/30
Abstract: A method of manufacturing a capacitor for a semiconductor device and a capacitor using the same are provided to improve contact between molten solder and external electrodes by forming OSP(Organic Solderability Preservation) coating films on copper electrodes of a laminate of dielectric sheets. A method of manufacturing a capacitor for a semiconductor device includes the steps of: forming a laminate of a plurality of dielectric sheets on which internal electrodes are printed(S20); forming external electrodes on side surfaces of the laminate to be electrically connected to the internal electrodes(S40); and forming OSP coating films on the external electrodes to prevent oxidation of the external electrodes(S50). The external electrode contains copper, and the OSP coating film contains alkylbenzimidazole.
Abstract translation: 提供一种制造用于半导体器件的电容器和使用其的电容器的方法，以通过在电介质片层叠体的铜电极上形成OSP（有机可焊性保存）涂层来改善熔融焊料和外部电极之间的接触。 制造半导体器件的电容器的方法包括以下步骤：形成印刷有内部电极的多个电介质片材的层叠体（S20）。 在所述层叠体的侧面形成外部电极以与所述内部电极电连接（S40）; 并在外部电极上形成OSP涂层以防止外部电极氧化（S50）。 外部电极含有铜，OSP涂膜含有烷基苯并咪唑。
-
Patent Agency Ranking
公开(公告)号：KR100809711B1
公开(公告)日：2008-03-06
申请号：KR1020060109070
申请日：2006-11-06
Applicant: 삼성전자주식회사
IPC: H01L27/02
CPC classification number: H05K3/3442 , H05K1/111 , H05K1/181 , H05K3/06 , H05K3/244 , H05K2201/09736 , H05K2201/10477 , H05K2201/10636 , H05K2203/0369 , Y02P70/611 , Y02P70/613 , Y10T29/49133
Abstract: A semiconductor memory module with a chip resistor reversely mounted is provided to prevent electrical open defect due to the damage of a resistance by protecting a resistance element. A chip resistor(20) comprises an insulating substrate(22), a resistance element part on the insulating substrate, and a metal electrode(26). The metal electrode is electrically connected to the resistor part and arranged on the insulating substrate. A connecting pad(12a) of the chip resistor is formed higher than another connecting pad of a module substrate so that the resistance part of the chip resistor is not touched to the module substrate. An insulating dam is arranged between the connecting pads of the chip resistor on the module substrate to prevent a short. The resistance element part of the chip resistor includes a thin film resistance on the insulating substrate and a protective layer on the thin film resistance.
Abstract translation: 提供了一种具有反向安装的片式电阻器的半导体存储器模块，以通过保护电阻元件来防止由于电阻的损坏导致的电开路缺陷。 芯片电阻器（20）包括绝缘基板（22），绝缘基板上的电阻元件部分和金属电极（26）。 金属电极电连接到电阻器部分并且布置在绝缘基板上。 芯片电阻器的连接焊盘（12a）形成为高于模块基板的另一连接焊盘，使得芯片电阻器的电阻部分未被接触到模块基板。 在模块基板上的芯片电阻的连接焊盘之间设置绝缘水坝，以防止短路。 片式电阻器的电阻元件部分包括绝缘基板上的薄膜电阻和薄膜电阻上的保护层。
-
公开(公告)号：KR1020070062079A
公开(公告)日：2007-06-15
申请号：KR1020050121785
申请日：2005-12-12
Applicant: 삼성전자주식회사
CPC classification number: H05K3/1216 , H05K1/0266 , H05K3/18 , H05K3/281
Abstract: A printed circuit board having a position aligning mark and a manufacturing method thereof are provided to perform uniform solder printing by not protruding the position aligning mark from a photosensitive insulation layer. A metal circuit wiring is formed on at least one surface of a printed circuit board. A photosensitive insulation layer is formed on the metal circuit pattern. A position aligning mark(29) encloses a side of the photosensitive insulation layer, and an upper surface of the position aligning mark is exposed at a position lower than a height of the photosensitive insulation layer to guide a mounting position of an electronic component. The position aligning mark is a plating layer.
Abstract translation: 提供具有位置对准标记的印刷电路板及其制造方法，以通过不从光敏绝缘层突出位置对准标记来进行均匀的焊料印刷。 在印刷电路板的至少一个表面上形成金属电路布线。 在金属电路图案上形成感光绝缘层。 位置对准标记（29）包围光敏绝缘层的一侧，并且位置对准标记的上表面在比感光绝缘层的高度低的位置处露出，以引导电子部件的安装位置。 位置对准标记是镀层。
-
公开(公告)号：KR1020140027792A
公开(公告)日：2014-03-07
申请号：KR1020120093845
申请日：2012-08-27
Applicant: 삼성전자주식회사
CPC classification number: G11C16/30 , G11C5/147 , G11C16/32 , G11C2207/2227
Abstract: A solid state drive according to an embodiment of the present invention comprises: a clock generator for generating a first and a second clock signal; a first buck regulator for generating a first current in response to the first clock signal; a second buck regulator for generating a second current in response to the second clock signal; and a main power unit, in which the first and the second clock signal are generated in complementary to each other, which repeatedly receives the first and the second current sequentially in response to the first and the second clock signal.
Abstract translation: 根据本发明的实施例的固态驱动器包括：时钟发生器，用于产生第一和第二时钟信号; 第一降压调节器，用于响应于所述第一时钟信号产生第一电流; 第二降压调节器，用于响应于所述第二时钟信号产生第二电流; 以及主电源单元，其中第一和第二时钟信号彼此互补地产生，其响应于第一和第二时钟信号重复地接收第一和第二电流。
-
公开(公告)号：KR1020070048950A
公开(公告)日：2007-05-10
申请号：KR1020050106066
申请日：2005-11-07
Applicant: 삼성전자주식회사
CPC classification number: H05K3/0044 , H05K1/115 , H05K3/421
Abstract: 본 발명은 도금선이 내층에 형성된 반도체 모듈용 인쇄회로기판에 관한 것이다. 도금선이 기판의 표면에 형성된 종래의 인쇄회로기판은 소켓에 삽입될 때 도금선이 부러지는 경우가 발생된다. 부러진 도금선은 인접한 탭 단자 사이에 단락을 발생시키거나 탭 단자에 긁힘을 유발할 수 있다. 이와 같은 문제점을 해결하기 위하여, 본 발명은 탭 단자의 도금을 위하여 제공되는 도금선이 기판의 내층에 형성된 반도체 모듈용 인쇄회로기판을 제공한다. 본 발명에 따르면, 인쇄회로기판이 소켓에 삽입될 때 도금선과 소켓간의 물리적인 접촉이 이루어지지 않는다. 도금선의 부러짐으로 인한 탭 단자간의 단락이나 탭 단자의 긁힘이 방지된다. 따라서, 반도체 모듈 제품의 외관 불량 발생이 방지되고 제품 신뢰성이 향상된다.
반도체 모듈, 인쇄회로기판, 도금선(tie bar), 탭 단자, 소켓, 내층, 비아-
公开(公告)号：KR1020170028096A
公开(公告)日：2017-03-13
申请号：KR1020150124946
申请日：2015-09-03
Applicant: 삼성전자주식회사
CPC classification number: G01R31/40 , G01R19/16538 , G01R31/028 , G01R31/3631 , H02J7/0093 , H02J9/00
Abstract: 보조전원검사방법및 이를적용한전자장치에관하여개시한다. 보조전원검사방법은보조전원공급장치의충전동작을초기설정된시간동안중단시키기위한충전디스에이블신호를상기보조전원공급장치에인가하는단계, 상기충전디스에이블신호가인가되는구간에서상기보조전원공급장치의충전전압을모니터링하는단계및, 상기충전전압이초기설정된임계전압미만으로검출되는경우에상기보조전원공급장치를불량으로판정하는단계를포함하고, 상기보조전원공급장치는서든파워오프시에상기충전전압에기초한보조전원을시스템전원라인에공급하는것을특징으로한다.
Abstract translation: 提供了辅助电源测试方法和应用其的电子设备。 辅助电源测试方法包括：向辅助电源单元施加将辅助电源单元的充电操作中断预定时间段的充电禁止信号; 在对辅助电源单元施加充电禁止信号的时间间隔内监视辅助电源单元的充电电压; 基于所监视的充电电压是否小于预定阈值电压，确定辅助电源单元是否有故障，其中辅助电源单元将基于充电电压获得的辅助电力提供给系统电源线， 突然断电的情况。
-
-
-
-
-
Search Results
6
records
(took 0.018 seconds)
