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公开(公告)号：KR1020050062826A
公开(公告)日：2005-06-28
申请号：KR1020030093130
申请日：2003-12-18
Applicant: 삼성전자주식회사
IPC: H05K1/02
CPC classification number: H01R12/722 , H05K1/0268
Abstract: 본 발명은 외부 접촉 탭에 구멍이 형성된 인쇄 회로 기판에 관한 것으로서, 인쇄 회로 기판을 테스트 소켓에 삽입하여 테스트할 때 외부 접촉 탭과 소켓 리드 사이의 접촉 불량에 따른 문제를 해결하기 위한 것이다. 본 발명의 인쇄 회로 기판은 한쪽 가장자리에 일렬로 배열된 복수개의 외부 접촉 탭을 포함하며, 각각의 외부 접촉 탭은 원형의 접촉 구멍을 포함한다. 접촉 구멍은 소켓 리드와 원형 접촉을 이루므로 기존의 점 접촉에 비하여 접촉 면적이 증가하고 밀착성이 높아져 전기적 접촉성이 향상된다. 따라서, 재테스트 비율이 현저하게 줄어들며 생산 시간이 단축되는 효과가 있다.
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公开(公告)号：KR1020120107176A
公开(公告)日：2012-10-02
申请号：KR1020110024705
申请日：2011-03-21
Applicant: 삼성전자주식회사
CPC classification number: H01R12/7005 , H01R12/718 , G11B33/12 , H01R12/721
Abstract: PURPOSE: A data storage device and a manufacturing method thereof are provided to form a guide for guiding an insertion direction of a cable through a process which arranges an insulating material on a dummy tab, thereby inexpensively the data storage device without a separate connector. CONSTITUTION: A memory chip(120) is mounted on a PCB(Printed Circuit Board)(110). A connection tab(142) is formed on a first side of the PCB and connects the PCB to a cable. A dummy tab(144) is formed on a first side of the PCB. A guide(148) is formed on the dummy tab and guides an insertion direction of the cable. The cable includes an SATA(Serial Advanced Technology Attachment) cable. The connection tab is formed between a pair of guide members.
Abstract translation: 目的：提供一种数据存储装置及其制造方法，以形成用于通过将绝缘材料布置在虚拟标签上的处理来引导电缆的插入方向的引导件，从而廉价地提供没有单独的连接器的数据存储装置。 构成：存储芯片（120）安装在PCB（印刷电路板）（110）上。 连接片（142）形成在PCB的第一侧上，并将PCB连接到电缆。 在PCB的第一侧上形成虚拟凸片（144）。 引导件（148）形成在虚拟翼片上并引导电缆的插入方向。 电缆包括一个SATA（串行高级技术附件）电缆。 连接片形成在一对引导构件之间。
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公开(公告)号：KR100837276B1
公开(公告)日：2008-06-11
申请号：KR1020060131083
申请日：2006-12-20
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H05K1/147 , G11C5/04 , H01L2224/16225 , H05K1/117 , H05K1/189 , H05K3/4691 , H05K2201/042 , H05K2201/10159 , H05K2201/2009 , H05K2203/1572
Abstract: A printed circuit board and a semiconductor memory module using the same are provided to increase integration density of a memory device by enlarging an implementation space of the semiconductor memory module. A printed circuit board includes a rigid PCB(Printed Circuit Board) portion(110) and an FPCB portion(130). The rigid PCB portion has first and second surfaces. The second surface is opposed to the first surface. The FPCB(Flexible Printed Circuit Board) portion has an overlap portion and a non-overlap portion. The overlap portion is overlapped with the rigid PCB portion, while the non-overlap portion is not overlapped with the rigid PCB portion. The FPCB portion has a lamination structure having at least one hemispheric curved portion.
Abstract translation: 提供一种印刷电路板和使用其的半导体存储器模块，以通过扩大半导体存储器模块的实现空间来增加存储器件的集成密度。 印刷电路板包括刚性PCB（印刷电路板）部分（110）和FPCB部分（130）。 刚性PCB部分具有第一和第二表面。 第二表面与第一表面相对。 FPCB（柔性印刷电路板）部分具有重叠部分和非重叠部分。 重叠部分与刚性PCB部分重叠，而非重叠部分不与刚性PCB部分重叠。 FPCB部分具有至少一个半球形弯曲部分的层叠结构。
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公开(公告)号：KR100723489B1
公开(公告)日：2007-05-31
申请号：KR1020050052485
申请日：2005-06-17
Applicant: 삼성전자주식회사
CPC classification number: H05K3/244 , H01L2924/0002 , H05K3/243 , H05K3/28 , H05K3/282 , H05K3/427 , H05K2201/0391 , H05K2203/0574 , H01L2924/00
Abstract: 신뢰성을 개선할 수 있는 반도체 장치 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명에 의한 반도체 장치는 모듈용 인쇄회로기판의 패드 표면에 OSP(Organic Solderability Preservative) 처리를 하고, 관통홀 측벽에는 니켈 및 금 도금층을 형성한다. 따라서 온도변화에 따른 신뢰성 검사(temperature cycle)에서 관통홀 내부에서 발생하는 크랙(crack)과 같은 결함을 억제할 수 있다.
신뢰성 검사, 인쇄회로기판, 관통홀, OSP.-
5.发明授权반도체 저항 요소, 상기 반도체 저항 요소를 포함하는 반도체 모듈, 및 상기 반도체 모듈을 포함하는 프로세서 베이스드 시스템 有权半导体电阻元件半导体模块，包括半导体电阻元件和包括半导体模块的基于处理器的系统
公开(公告)号：KR101638562B1
公开(公告)日：2016-07-11
申请号：KR1020100018084
申请日：2010-02-26
Applicant: 삼성전자주식회사
IPC: H01L27/02
CPC classification number: H01L28/20 , H01L23/48 , H01L27/13 , H01L2924/0002 , H01L2924/00
Abstract: 반도체저항요소를제공할수 있다. 이를위해서, 절연기판이준비될수 있다. 상기절연기판상에저항패턴들을형성할수 있다. 상기저항패턴들은서로에대해서직각을이루는평면들상에배치될수 있다. 상기저항패턴들상에전극들이배치될수 있다. 상기전극들의일 단들은저항패턴들과전기적으로접속할수 있다. 상기전극들의타 단들은선택된평면상에위치할수 있다. 상기반도체저항요소는반도체모듈상에배치될수 있다. 상기반도체모듈은프로세서베이스드시스템(Processor-based system)에배치될수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020070111886A
公开(公告)日：2007-11-22
申请号：KR1020060045279
申请日：2006-05-19
Applicant: 삼성전자주식회사
CPC classification number: H05K1/185 , H05K3/3436 , H05K3/3452 , H05K3/4697
Abstract: A printed circuit board for surface mount and a method for forming the same are provided to increase a degree of integration by arranging a part or the whole of a passive element to be covered with a semiconductor package. A printed circuit board for surface mount includes a passive element(150) and a semiconductor package(160). The passive element is buried in a printed circuit board(110) and is protruded from an upper part of the printed circuit board. The semiconductor package is mounted on an upper part of the printed circuit board. A part or an entire part of the passive element is overlapped with the semiconductor package. The semiconductor package is mounted on the printed circuit board by solder balls(165). The passive element is buried in a non-penetrating hole(120) of the printed circuit board.
Abstract translation: 提供了一种用于表面贴装的印刷电路板及其形成方法，以通过将半导体封装件覆盖的无源元件的一部分或全部布置来增加集成度。 用于表面贴装的印刷电路板包括无源元件（150）和半导体封装（160）。 无源元件被埋在印刷电路板（110）中并且从印刷电路板的上部突出。 半导体封装安装在印刷电路板的上部。 无源元件的一部分或全部与半导体封装重叠。 半导体封装通过焊球（165）安装在印刷电路板上。 无源元件被埋在印刷电路板的非穿透孔（120）中。
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公开(公告)号：KR1020060132247A
公开(公告)日：2006-12-21
申请号：KR1020050052485
申请日：2005-06-17
Applicant: 삼성전자주식회사
CPC classification number: H05K3/244 , H01L2924/0002 , H05K3/243 , H05K3/28 , H05K3/282 , H05K3/427 , H05K2201/0391 , H05K2203/0574 , H01L2924/00
Abstract: A semiconductor apparatus with an improved reliability and a method for manufacturing the same are provided to suppress a crack in a temperature cycle according to a temperature variation by treating a pad surface of a printed circuit board with an OSP process and forming a nickel and gold plating layer on a lateral side of a through hole. In a semiconductor apparatus with an enhanced reliability, a printed circuit board(142) includes a pad formed on a surface of an insulation material and a through hole(150) penetrating the insulation material up and down. A surface of the pad of the printed circuit board(142) is treated with an OSP(Organic Solderability Preservative) process and a lateral side of the through hole(150) is treated with a gold plating. A semiconductor element is mounted on an upper side of the printed circuit board(142) though the pad.
Abstract translation: 提供一种可靠性提高的半导体装置及其制造方法，用于通过用OSP工艺处理印刷电路板的焊盘表面以形成镍和镀金电镀来根据温度变化来抑制温度循环中的裂纹 层在通孔的侧面上。 在具有增强的可靠性的半导体装置中，印刷电路板（142）包括形成在绝缘材料的表面上的焊盘和上下穿透绝缘材料的通孔（150）。 用OSP（有机可焊性防腐剂）处理印刷电路板（142）的焊盘的表面，并用镀金处理通孔（150）的侧面。 半导体元件通过焊盘安装在印刷电路板（142）的上侧。
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公开(公告)号：KR1020080073506A
公开(公告)日：2008-08-11
申请号：KR1020070012206
申请日：2007-02-06
Applicant: 삼성전자주식회사
IPC: H01L23/02 , H01L27/108 , H05K1/02
CPC classification number: H05K1/0207 , H05K1/056 , H05K3/4641 , H05K2201/0919 , H05K2201/10159 , H05K2201/1056 , H05K2203/1572
Abstract: A printed circuit board and a semiconductor memory module using the same are provided to effectively radiate heat from the semiconductor memory module to the outside by applying a PCB(Printed Circuit Board) with a metal core on the semiconductor memory module. A printed circuit board includes a board unit(110) and a metal core(130). The board unit includes first and second surfaces, which are opposed to each other. The metal core includes an insertion portion(130i) and an elongation portion(130e). The insertion portion is inserted into an inner portion of the board unit. The elongation portion is elongated from at least one side portion of the board unit. The elongation portions of a pair of metal cores are elongated from both sides of the board unit, respectively. The metal core contains a thermally conductive material, which is selected from the group consisting of aluminum, copper, silver, and gold.
Abstract translation: 提供一种印刷电路板和使用其的半导体存储器模块，以通过在半导体存储器模块上施加具有金属芯的PCB（印刷电路板）来有效地将热量从半导体存储器模块辐射到外部。 印刷电路板包括板单元（110）和金属芯（130）。 板单元包括彼此相对的第一和第二表面。 金属芯包括插入部（130i）和伸长部（130e）。 插入部插入到板单元的内部。 伸长部分从板单元的至少一个侧部伸长。 一对金属芯的伸长部分分别从板单元的两侧伸长。 金属芯包含导热材料，其选自铝，铜，银和金。
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公开(公告)号：KR1020080061719A
公开(公告)日：2008-07-03
申请号：KR1020060136734
申请日：2006-12-28
Applicant: 삼성전자주식회사
IPC: H01G4/30
Abstract: A method of manufacturing a capacitor for a semiconductor device and a capacitor using the same are provided to improve contact between molten solder and external electrodes by forming OSP(Organic Solderability Preservation) coating films on copper electrodes of a laminate of dielectric sheets. A method of manufacturing a capacitor for a semiconductor device includes the steps of: forming a laminate of a plurality of dielectric sheets on which internal electrodes are printed(S20); forming external electrodes on side surfaces of the laminate to be electrically connected to the internal electrodes(S40); and forming OSP coating films on the external electrodes to prevent oxidation of the external electrodes(S50). The external electrode contains copper, and the OSP coating film contains alkylbenzimidazole.
Abstract translation: 提供一种制造用于半导体器件的电容器和使用其的电容器的方法，以通过在电介质片层叠体的铜电极上形成OSP（有机可焊性保存）涂层来改善熔融焊料和外部电极之间的接触。 制造半导体器件的电容器的方法包括以下步骤：形成印刷有内部电极的多个电介质片材的层叠体（S20）。 在所述层叠体的侧面形成外部电极以与所述内部电极电连接（S40）; 并在外部电极上形成OSP涂层以防止外部电极氧化（S50）。 外部电极含有铜，OSP涂膜含有烷基苯并咪唑。
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公开(公告)号：KR100809711B1
公开(公告)日：2008-03-06
申请号：KR1020060109070
申请日：2006-11-06
Applicant: 삼성전자주식회사
IPC: H01L27/02
CPC classification number: H05K3/3442 , H05K1/111 , H05K1/181 , H05K3/06 , H05K3/244 , H05K2201/09736 , H05K2201/10477 , H05K2201/10636 , H05K2203/0369 , Y02P70/611 , Y02P70/613 , Y10T29/49133
Abstract: A semiconductor memory module with a chip resistor reversely mounted is provided to prevent electrical open defect due to the damage of a resistance by protecting a resistance element. A chip resistor(20) comprises an insulating substrate(22), a resistance element part on the insulating substrate, and a metal electrode(26). The metal electrode is electrically connected to the resistor part and arranged on the insulating substrate. A connecting pad(12a) of the chip resistor is formed higher than another connecting pad of a module substrate so that the resistance part of the chip resistor is not touched to the module substrate. An insulating dam is arranged between the connecting pads of the chip resistor on the module substrate to prevent a short. The resistance element part of the chip resistor includes a thin film resistance on the insulating substrate and a protective layer on the thin film resistance.
Abstract translation: 提供了一种具有反向安装的片式电阻器的半导体存储器模块，以通过保护电阻元件来防止由于电阻的损坏导致的电开路缺陷。 芯片电阻器（20）包括绝缘基板（22），绝缘基板上的电阻元件部分和金属电极（26）。 金属电极电连接到电阻器部分并且布置在绝缘基板上。 芯片电阻器的连接焊盘（12a）形成为高于模块基板的另一连接焊盘，使得芯片电阻器的电阻部分未被接触到模块基板。 在模块基板上的芯片电阻的连接焊盘之间设置绝缘水坝，以防止短路。 片式电阻器的电阻元件部分包括绝缘基板上的薄膜电阻和薄膜电阻上的保护层。
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