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    콘택 플러그를 포함하는 반도체 소자
    3.
    发明公开
    콘택 플러그를 포함하는 반도체 소자 有权
    具有接触插头的半导体器件

    公开(公告)号：KR1020120001897A

    公开(公告)日：2012-01-05

    申请号：KR1020100062512

    申请日：2010-06-30

    Applicant: 삼성전자주식회사

    Inventor： 채교석 ,  야마다,사토루 ,  한상연 ,  최영진 ,  김욱제

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833 ,  H01L29/4232

    Abstract: PURPOSE: A semiconductor device including a contact plug is provided to obtain high reliability and integration by increasing an amount of turn-on currents of a field effect transistor by widening an active area. CONSTITUTION: A device isolation pattern(102) is arranged on a substrate to define an active area(ACT). A gate electrode(110) is arranged on the upper side of the active area. A capping dielectric pattern is arranged on the gate electrode. A first source/drain area(122) and a second source/drain area(124) are formed in the active area of both sides of the gate electrode. An interlayer dielectric layer(130) is arranged on the substrate including the gate electrode.

    Abstract translation: 目的：提供一种包括接触插头的半导体器件，通过增加有源区域来增加场效应晶体管的导通电流量，从而获得高可靠性和集成度。 构成：器件隔离图案（102）布置在衬底上以限定有源区（ACT）。 栅电极（110）设置在有源区的上侧。 在栅极电极上设置覆盖电介质图案。 在栅电极的两侧的有源区域中形成有第一源极/漏极区域（122）和第二源极/漏极区域（124）。 在包括栅电极的基板上布置有层间绝缘层（130）。

    소자 분리 구조물을 갖는 반도체 소자
    4.
    发明公开
    소자 분리 구조물을 갖는 반도체 소자 有权
    具有器件隔离结构的半导体器件

    公开(公告)号：KR1020110052206A

    公开(公告)日：2011-05-18

    申请号：KR1020090109152

    申请日：2009-11-12

    Applicant: 삼성전자주식회사

    Inventor： 한승욱 ,  야마다,사토루 ,  최영진

    IPC: H01L21/762

    CPC classification number: H01L21/823481 ,  H01L21/76229 ,  H01L21/823425

    Abstract: PURPOSE: A semiconductor device with a device separating structure is provided to suppress holes from being induced into an active area by thermal electrons trapped in a nitride film pattern, thereby preventing the leaked currents of a PMOS transistor from increasing. CONSTITUTION: A semiconductor substrate(100) comprises a trench(103) defining active areas. A buried insulating film(142) is formed in the trench. An oxide film is formed between the buried insulating film and the trench. A nitride film is formed between the oxide film and the buried insulating film. A barrier film is formed between the oxide film and the nitride film.

    Abstract translation: 目的：提供一种具有器件分离结构的半导体器件，以通过捕获在氮化物膜图案中的热电子来抑制空穴被诱发到有源区域，从而防止PMOS晶体管的泄漏电流增加。 构成：半导体衬底（100）包括限定有源区的沟槽（103）。 在沟槽中形成掩埋绝缘膜（142）。 在掩埋绝缘膜和沟槽之间形成氧化膜。 在氧化膜和掩埋绝缘膜之间形成氮化膜。 在氧化膜和氮化物膜之间形成阻挡膜。

    반도체 기억 소자
    6.
    发明公开
    반도체 기억 소자 审中-实审
    半导体存储器件

    公开(公告)号：KR1020130109821A

    公开(公告)日：2013-10-08

    申请号：KR1020120031870

    申请日：2012-03-28

    Applicant: 삼성전자주식회사

    Inventor： 전남호 ,  김준수 ,  야마다,사토루 ,  이재훈 ,  한승욱 ,  김지영 ,  이진성

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L29/7831 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L21/28273

    Abstract: PURPOSE: A semiconductor memory device has improved data retention characteristics by preventing junction leakage and/or recombination caused by PN junction. CONSTITUTION: A write transistor (WTr) includes a first write gate (WG1) controlling first source and drain terminals and a second write gate (WG2) controlling a channel region. The first write gate has a first work function. The second write gate has a second work function different from the first work function. The first source and drain terminals of the write transistor do not have PN junction. A read transistor (RTr) includes a memory node gate (MNG) connected to the first source and drain terminals of the write transistor. The memory node gate is arranged between a control gate (RCG) and the channel region of the read transistor.

    Abstract translation: 目的：半导体存储器件通过防止由PN结引起的结漏电和/或复合，具有改善的数据保留特性。 构成：写入晶体管（WTr）包括控制第一源极和漏极端子的第一写入栅极（WG1）和控制沟道区域的第二写入栅极（WG2）。 第一个写入口具有第一个工作功能。 第二写入门具有与第一功能不同的第二功能。 写入晶体管的第一个源极和漏极端子没有PN结。 读取晶体管（RTr）包括连接到写入晶体管的第一源极和漏极端子的存储器节点栅极（MNG）。 存储节点门被布置在控制栅（RCG）和读晶体管的沟道区之间。

    반도체 소자
    7.
    发明公开
    반도체 소자 有权
    半导体器件

    公开(公告)号：KR1020110094476A

    公开(公告)日：2011-08-24

    申请号：KR1020100013873

    申请日：2010-02-16

    Applicant: 삼성전자주식회사

    Inventor： 박원경 ,  야마다,사토루 ,  최영진 ,  채교석

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/105 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    Abstract: PURPOSE: A semiconductor device is provided to suppress HEIP(Hot Electron Induced Punch-through) characteristic deterioration by forming an insertion pattern removing adjacent nitride linear to a gate electrode. CONSTITUTION: In a semiconductor device, a substrate comprises a cell area and a peripheral area. The cell region comprises a cell active pattern(CA) and a cell filed pattern(CF). The peripheral area comprises a peripheral cell region and a peripheral filed pattern. A first transistor(TR 1) is formed in the cell region. An insertion pattern(IP) is recessed from the surface of the substrate.

    Abstract translation: 目的：提供一种半导体器件，用于通过形成去除与栅电极线性相邻的氮化物的插入图案来抑制HEIP（热电子诱发穿通）特性劣化。 构成：在半导体器件中，衬底包括电池区域和周边区域。 小区区域包括小区活动模式（CA）和小区归属模式（CF）。 外围区域包括外围单元区域和外围区域图案。 在单元区域中形成第一晶体管（TR 1）。 插入图案（IP）从衬底的表面凹陷。

    반도체 소자 및 그 제조 방법
    10.
    发明公开
    반도체 소자 및 그 제조 방법 审中-实审
    SMICONDUCTOR DEVICE AND METHOD OF FABRISTING THE SAME

    公开(公告)号：KR1020150117770A

    公开(公告)日：2015-10-21

    申请号：KR1020140043151

    申请日：2014-04-10

    Applicant: 삼성전자주식회사

    Inventor： 이성삼 ,  야마다,사토루 ,  조민희

    IPC: H01L21/336 ,  H01L21/316 ,  H01L29/78

    CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/76229

    Abstract: 반도체소자및 그제조방법이제공된다. 반도체소자의제조방법은기판상에트렌치를형성하는것; 상기트렌치내에제1 산화막을형성하는것; 상기제1 산화막상에제2 산화막을형성하되, 상기제2 산화막은상기제1 산화막보다치밀한것; 상기제2 산화막상에제3 산화막을형성하는것; 및상기제3 산화막상에제공되며, 상기트렌치를채우는절연패턴을형성하는것을포함할수 있다.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件的制造方法包括以下步骤：在衬底上形成沟槽; 在沟槽中形成第一氧化膜; 在所述第一氧化物膜上形成第二氧化物膜，其中所述第二氧化物膜比所述第一氧化物膜更致密; 在所述第二氧化物膜上形成第三氧化物膜; 以及提供提供给第三氧化膜的绝缘图案，其中沟槽填充有绝缘图案。

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