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公开(公告)号：KR1020040022356A
公开(公告)日：2004-03-12
申请号：KR1020020053632
申请日：2002-09-05
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A method for fabricating a gate electrode of a non-volatile memory(NVM) device is provided to guarantee an electrical characteristic in inputting and removing a program of the NVM device and reduce the size of the NVM device by making a floating gate with a sharp tip. CONSTITUTION: A mask layer is formed on a conductive layer formed on a substrate(100). A part of the mask layer is etched by the first etch process to form the first mask pattern that doesn't expose the conductive layer and has a vertical profile. The mask layer that is not etched by the first etch process is etched by the second etch process so as to form the second mask pattern exposing the conductive layer. The third etch process using nitrofluoride-based etch gas and oxygen-based etch gas is performed on the conductive layer having the second mask pattern so as to form the floating gate with a sharp tip while the substrate is not exposed.
Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的栅电极的方法，以保证在输入和移除NVM器件的程序时的电气特性，并通过制作浮置栅极来减小NVM器件的尺寸 一个尖锐的提示。 构成：在形成在基板（100）上的导电层上形成掩模层。 通过第一蚀刻工艺蚀刻掩模层的一部分以形成不暴露导电层并具有垂直轮廓的第一掩模图案。 通过第二蚀刻工艺蚀刻未被第一蚀刻工艺蚀刻的掩模层，以形成露出导电层的第二掩模图案。 在具有第二掩模图案的导电层上进行使用基于硝基氟化物的蚀刻气体和氧基蚀刻气体的第三蚀刻工艺，以便在不暴露衬底的同时形成具有尖锐尖端的浮动栅极。
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公开(公告)号：KR1020000021057A
公开(公告)日：2000-04-15
申请号：KR1019980039988
申请日：1998-09-25
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method of forming a metal wiring is provided to reduce the number of steps increased due to a metal layer of multi-layer. CONSTITUTION: A passivation layer(12) such as a SiO2 layer or a NO2 layer is formed on a silicon substrate(11) to prevent the substrate. After removing a portion of the passivation layer by using an etching process, a diffusion barrier layer(13) is formed on a surface of the passivation layer as well as the etched portion. A tungsten layer(14) is formed on the diffusion barrier layer to be filled into the removed area of the passivation layer. A diffusion barrier layer(15) is formed on the tungsten layer. A metal layer(16) of a conductive material is formed on the barrier layer, and is etched by using a lithography. A photoresist layer is formed in a position to form a metal wiring. The photoresist layer is positioned on an upper portion of the tungsten layer.
Abstract translation: 目的：提供一种形成金属布线的方法，以减少由于多层金属层而增加的台阶数。 构成：在硅衬底（11）上形成诸如SiO 2层或NO 2层的钝化层（12）以防止衬底。 在通过使用蚀刻工艺去除钝化层的一部分之后，在钝化层的表面和蚀刻部分上形成扩散阻挡层（13）。 在扩散阻挡层上形成钨层（14），以将其填充到钝化层的去除区域中。 在钨层上形成扩散阻挡层（15）。 导电材料的金属层（16）形成在阻挡层上，并通过光刻进行蚀刻。 光致抗蚀剂层形成在形成金属布线的位置。 光致抗蚀剂层位于钨层的上部。
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公开(公告)号：KR100844978B1
公开(公告)日：2008-07-09
申请号：KR1020020043967
申请日：2002-07-25
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: 반도체 메모리 장치의 게이트 전극 형성 방법이 개시되어 있다. 제1산화막 패턴, 도전막 패턴 및 제2산화막 패턴들이 연속적으로 스탠딩되어 형성된 기판 상에 균일한 두께를 갖는 폴리막을 형성한다. 상기 결과물을 연마하여 상기 제1산화막 패턴, 도전막 패턴 및 제2산화막 패턴의 각각의 표면을 노출시킨다. 상기 표면이 노출된 도전막 패턴과 상기 폴리막 패턴의 소정영역 상에 제3산화막을 형성한다. 상기 제3산화막과 상기 표면이 노출된 제1산화막 패턴 및 제2산화막 패턴을 식각 마스크로 사용하고, 상기 제3산화막과 상기 폴리막 패턴의 식각 선택비가 1: 9 내지 15를 갖는 식각 소스를 사용하여 상기 폴리막 패턴을 식각한다. 상기 식각 공정을 적용하여 형성된 반도체 장치의 식각 프로파일 우수한 게이트 전극은 상기 메모리 장치의 전기적 특성을 향상시킬 수 있다.
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公开(公告)号：KR100487547B1
公开(公告)日：2005-05-03
申请号：KR1020020055292
申请日：2002-09-12
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11521 , H01L27/115
Abstract: 비휘발성 메모리 장치의 제조 방법을 제공한다. 이 방법은 반도체기판 상에 하부 도전막을 형성하고, 그 결과물 상에 차례로 적층된 하부 희생막 패턴 및 상부 희생막 패턴을 형성한 후, 상부 및 하부 희생막 패턴의 측벽에 마스크 스페이서를 형성하는 단계를 포함한다. 이때, 상부 및 하부 희생막 패턴은 하부 도전막을 노출시키는 개구부를 갖는다. 또한, 상부 희생막 패턴은 하부 희생막 패턴에 대해 식각 선택성을 갖는 물질, 바람직하게는 실리콘 산화막으로 형성한다. 이때, 상부 희생막 패턴은 저온 화학 기상 증착의 방법으로 형성하는 것이 바람직하다. 그 결과, 열적 부담없이 마스크 스페이서의 높이를 증가시킬 수 있기 때문에, 워드 라인과 소오스 라인 사이의 쇼트를 예방할 수 있다.
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公开(公告)号：KR1020040023857A
公开(公告)日：2004-03-20
申请号：KR1020020055292
申请日：2002-09-12
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11521 , H01L27/115
Abstract: PURPOSE: A method for fabricating a non-volatile memory(NVM) device is provided to minimize thermal budget generated when a lower sacrificial layer is thickly formed, by forming an upper sacrificial layer made of a material like a silicon oxide layer having etch selectivity on the lower sacrificial layer. CONSTITUTION: A lower conductive layer is formed on a semiconductor substrate(100). A lower sacrificial layer pattern(135) having an opening exposing the lower conductive layer and an upper sacrificial layer pattern(145) are formed on the substrate including the lower conductive layer. A mask spacer(170) is formed on the sidewall of the upper and lower sacrificial layer patterns. The exposed lower conductive layer is etched by using the mask spacer and the upper sacrificial layer pattern as an etch mask so as to form a lower conductive layer pattern exposing the substrate. A plug conductive layer is formed to cover the front surface of the substrate including the lower conductive layer pattern. The plug conductive layer is planarization-etched until the lower sacrificial layer pattern is exposed, so that a source plug which fills a gap region between the mask spacers and is connected to the substrate is formed.
Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的方法，用于通过形成由诸如具有蚀刻选择性的氧化硅层的材料制成的上牺牲层来最小化当下牺牲层厚度形成时产生的热预算 下牺牲层。 构成：在半导体衬底（100）上形成下导电层。 在包括下导电层的基板上形成具有暴露下导电层的开口的下牺牲层图案（135）和上牺牲层图案（145）。 掩模间隔物（170）形成在上和下牺牲层图案的侧壁上。 通过使用掩模间隔物和上牺牲层图案作为蚀刻掩模来蚀刻暴露的下导电层，以形成露出衬底的下导电层图案。 形成插塞导电层以覆盖包括下导电层图案的基板的前表面。 插塞导电层被平坦化蚀刻，直到下部牺牲层图案露出，从而形成填充掩模间隔物之间的间隙区域并与衬底连接的源极插塞。
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Patent Agency Ranking
公开(公告)号：KR1020040010927A
公开(公告)日：2004-02-05
申请号：KR1020020043967
申请日：2002-07-25
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A method for forming a gate electrode of a semiconductor memory device is provided to be capable of minimizing the damage of a hard mask and restraining the etching profile of a poly layer pattern from being damaged. CONSTITUTION: A floating gate structure is formed at the upper portion of a semiconductor substrate(50). The floating gate structure includes an oxide spacer, a floating gate, and a source line connected with a source region(52). The first oxide layer(62a) and a control gate poly layer(64a) are sequentially formed on the entire surface of the resultant structure. Then, a nitride layer is formed at the upper portion of the control gate poly layer. After carrying out a CMP(Chemical Mechanical Polishing) process at the resultant structure until the source line and the spacer are exposed, the second oxide layer(70) is formed at the upper portions of the source line and control gate poly layer as a hard mask. Then, a control gate is formed by selectively etching the control gate poly.
Abstract translation: 目的：提供一种用于形成半导体存储器件的栅电极的方法，其能够使硬掩模的损伤最小化并且抑制多层图案的蚀刻轮廓损坏。 构成：在半导体衬底（50）的上部形成浮栅结构。 浮置栅极结构包括氧化物间隔物，浮动栅极和与源极区域（52）连接的源极线。 第一氧化物层（62a）和控制栅极多层（64a）依次形成在所得结构的整个表面上。 然后，在控制栅极多层的上部形成氮化物层。 在所得到的结构中进行CMP（化学机械抛光）处理直到源极线和间隔物露出为止，第二氧化物层（70）形成在源极线和控制栅极多层的上部，作为硬 面具。 然后，通过选择性地蚀刻控制栅极poly形成控制栅极。
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7.发明公开
公开(公告)号：KR1020040077044A
公开(公告)日：2004-09-04
申请号：KR1020030012429
申请日：2003-02-27
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L29/66825 , H01L21/7684
Abstract: PURPOSE: A method for forming a conductive pattern of a semiconductor device and a method for fabricating a non-volatile memory device using the same are provided to enhance the reliability by improving a planarization degree of a semiconductor structure. CONSTITUTION: A conductive layer is formed on a semiconductor substrate(S11). A polishing stop layer is formed on the semiconductor substrate including the conductive layer(S12). A step compensation layer is formed on the polishing stop layer in order to reduce the step coverage of the polishing stop layer(S13). The conductive layer is exposed by removing partially the step compensation layer and the polishing stop layer. A conductive pattern is formed on the semiconductor substrate by etching the conductive layer(S14).
Abstract translation: 目的：提供一种用于形成半导体器件的导电图案的方法和使用其制造使用其的非易失性存储器件的方法，以通过提高半导体结构的平坦化程度来提高可靠性。 构成：在半导体基板上形成导电层（S11）。 在包括导电层的半导体衬底上形成抛光停止层（S12）。 为了减少抛光停止层的台阶覆盖，在抛光停止层上形成台阶补偿层（S13）。 导电层通过部分去除台阶补偿层和抛光停止层而暴露。 通过蚀刻导电层在半导体衬底上形成导电图案（S14）。
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公开(公告)号：KR1020040019705A
公开(公告)日：2004-03-06
申请号：KR1020020051402
申请日：2002-08-29
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A trench etching method for manufacturing a semiconductor chip is provided to be capable of preventing a bowing and trenching phenomenon for obtaining an aiming type trench. CONSTITUTION: An insulating layer is formed at the upper portion of a wafer. A trench pattern is formed at the predetermined portion of the insulating layer. A trench is formed on the wafer by carrying out an etching process on the resultant structure using the trench pattern. At this time, the etching process is carried out under a predetermined condition. The predetermined condition include a pressure of 50 mT, an HBr/Cl2 rate of 3 :1, and an He-O2 flow of 10%. Preferably, the width of the trench is 250 nm and the aspect ratio of the trench is 2 :5 :1.
Abstract translation: 目的：提供一种用于制造半导体芯片的沟槽蚀刻方法，以能够防止用于获得瞄准型沟槽的弯曲和开沟现象。 构成：在晶片的上部形成绝缘层。 在绝缘层的预定部分处形成沟槽图案。 通过使用沟槽图案对所得结构进行蚀刻处理，在晶片上形成沟槽。 此时，在预定条件下进行蚀刻处理。 预定条件包括压力为50mT，HBr / Cl2为3:1，He-O2流为10％。 优选地，沟槽的宽度为250nm，并且沟槽的纵横比为2:5:1。
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9.发明授权
公开(公告)号：KR100274597B1
公开(公告)日：2001-02-01
申请号：KR1019970019338
申请日：1997-05-19
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: PURPOSE: A plasma etch method using an etch gas composition of a polycrystalline silicon layer and a tungsten silicide layer is provided to improve an isotropic etch characteristic and etch selectivity regarding an oxide layer, by using an etch gas composition composed of chlorine gas and oxygen gas or etch gas composition composed of chlorine gas, inert gas and oxygen gas. CONSTITUTION: The etch gas composition composed of chlorine gas and oxygen gas is inserted into an etch chamber maintaining a pressure of 100 milliTorr. Power of 200 watt is supplied to the etch chamber to transform the etch gas composition to a plasma state. A magnetic field of 30 Gauss is formed inside the etch chamber to etch the tungsten silicide layer and the polycrystalline silicon layer(14) formed on the semiconductor substrate(10).
Abstract translation: 目的：提供使用多晶硅层和硅化钨层的蚀刻气体组合物的等离子体蚀刻方法，以通过使用由氯气和氧气组成的蚀刻气体组合来改善关于氧化物层的各向同性蚀刻特性和蚀刻选择性 或由氯气，惰性气体和氧气组成的蚀刻气体组成。 构成：将由氯气和氧气组成的蚀刻气体组合物插入保持100毫乇压力的蚀刻室中。 将200瓦的功率供应到蚀刻室以将蚀刻气体组合物转化为等离子体状态。 在蚀刻室内形成30高斯的磁场，以蚀刻形成在半导体衬底（10）上的硅化钨层和多晶硅层（14）。
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10.发明公开
公开(公告)号：KR1019980083860A
公开(公告)日：1998-12-05
申请号：KR1019970019338
申请日：1997-05-19
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: 본 발명은 등방성 식각특성 및 산화막에 대한 선택비가 뛰어난 반도체장치 제조용 다결정 규소막 및 텅스텐 실리사이드막의 식각가스 조성물과 이를 이용한 플라즈마 식각 방법에 관한 것이다.
본 발명은, 염소가스와 산소가스로 이루어지는 식각가스 조성물 또는 염소가스와 산화성가스로 이루어진 식각가스 조성물을 100 mT의 압력이 유지되는 식각챔버에 투입하는 단계; (2) 상기 (1)의 식각챔버에서 200 W의 전력을 공급하여 상기 식각가스 조성물을 플라즈마 상태로 변환하는 단계; 및 (3) 상기 (2)의 식각챔버 내부에 30 G의 자장을 형성시켜 반도체 기판 상에 형성된 텅스텐 실리사이드막 및 다결정 규소막을 식각하는 단계를 포함하여 이루어진다.
따라서, 등방성식각특성이 우수하고 산화막에 대한 선택비가 뛰어난 염소가스와 산소가스를 포함하는 식각가스 조성물을 사용하여 플라즈마 식각공정을 용이하게 수행할 수 있는 효과가 있다.
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