-
公开(公告)号：KR1020140007659A
公开(公告)日：2014-01-20
申请号：KR1020120075039
申请日：2012-07-10
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L23/5226 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76879 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68381 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/11462 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/16225 , H01L2224/19 , H01L2224/24011 , H01L2224/24051 , H01L2224/24147 , H01L2224/32145 , H01L2224/73209 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82106 , H01L2224/83005 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/06517 , H01L2225/06524 , H01L2225/06565 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
Abstract: A multi-chip package according to the present invention comprises a first semiconductor chip, a second semiconductor chip, an insulating film structure, and a plug structure. The first semiconductor chip includes first bonding pads. The second semiconductor chip is located on the first semiconductor chip and includes second bonding pads. The insulating film structure covers the first and second semiconductor chips. The plug structure, which is located inside the insulating film structure and placed apart from sides of the first and second semiconductor chips, is formed by using a plating process and connects the first bonding pad and second bonding pad electrically. Therefore, problems caused by a micro-bump forming process can be completely resolved.
Abstract translation: 根据本发明的多芯片封装包括第一半导体芯片，第二半导体芯片，绝缘膜结构和插头结构。 第一半导体芯片包括第一接合焊盘。 第二半导体芯片位于第一半导体芯片上并且包括第二接合焊盘。 绝缘膜结构覆盖第一和第二半导体芯片。 通过使用电镀工艺形成位于绝缘膜结构内并且与第一和第二半导体芯片的侧面隔开的插塞结构，并且电连接第一焊盘和第二焊盘。 因此，能够完全解决由微凸块形成工序引起的问题。
-
公开(公告)号：KR1020140041975A
公开(公告)日：2014-04-07
申请号：KR1020120106710
申请日：2012-09-25
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49811 , H01L23/49838 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/02331 , H01L2224/02351 , H01L2224/02372 , H01L2224/0345 , H01L2224/0381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05025 , H01L2224/05166 , H01L2224/05548 , H01L2224/0556 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/10165 , H01L2224/10175 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13008 , H01L2224/13015 , H01L2224/13017 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13147 , H01L2224/13164 , H01L2224/14133 , H01L2224/16105 , H01L2224/16145 , H01L2224/16235 , H01L2224/16238 , H01L2224/81191 , H01L2225/06513 , H01L2225/06517 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/01074 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2924/00
Abstract: A bump structure is provided. A body part which is separated from a pad on a substrate and at least one first extension part which is extended from one side of the body part onto the pad are provided. At least one second extension part which is extended from the other side of the body part is provided. The width of the first extension part is smaller than that of the body part.
Abstract translation: 提供凸块结构。 提供了与基板上的焊盘分离的主体部分和从主体部分的一侧延伸到焊盘上的至少一个第一延伸部分。 提供从身体部分的另一侧延伸的至少一个第二延伸部分。 第一延伸部的宽度小于主体部的宽度。
-
公开(公告)号：KR1020080052053A
公开(公告)日：2008-06-11
申请号：KR1020060124068
申请日：2006-12-07
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/49175 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor package including a ground conductor is provided to shorten a signal line path and a return path and reduce loop inductance by additionally installing a ground conductor on the lateral surface of a semiconductor chip and by using the ground conductor as a ground. A substrate(110) is used as a basic frame for fabricating a semiconductor package, made of an insulation material including a printed circuit pattern. A semiconductor chip(120) is mounted on a chip pad formed on the substrate. A ground conductor(130) is formed on the substrate, disposed on the lateral surface of the substrate separated from the semiconductor chip. A signal line pad of the semiconductor chip is connected to a bond finger(112) of the substrate by a first wire(140). A ground pad of the semiconductor chip is connected to the ground conductor by a second wire(142). The ground conductor can be connected to the printed circuit pattern for grounding the substrate by a soldering part.
Abstract translation: 提供包括接地导体的半导体封装，以通过在半导体芯片的侧表面上另外安装接地导体并且使用接地导体作为接地来缩短信号线路径和返回路径并减小回路电感。 基板（110）用作用于制造半导体封装的基本框架，其由包括印刷电路图案的绝缘材料制成。 半导体芯片（120）安装在形成在基板上的芯片焊盘上。 接地导体（130）形成在基板上，设置在与半导体芯片分离的基板的侧表面上。 半导体芯片的信号线焊盘通过第一线（140）连接到衬底的接合指状物（112）。 半导体芯片的接地焊盘通过第二导线（142）连接到接地导体。 接地导体可以连接到印刷电路图案，以通过焊接部件将基板接地。
-
公开(公告)号：KR1020130110959A
公开(公告)日：2013-10-10
申请号：KR1020120033341
申请日：2012-03-30
Applicant: 삼성전자주식회사
IPC: H01L23/488
CPC classification number: H01L24/14 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05022 , H01L2224/05099 , H01L2224/05568 , H01L2224/05599 , H01L2224/06102 , H01L2224/11452 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13012 , H01L2224/13014 , H01L2224/13018 , H01L2224/1308 , H01L2224/13099 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/17517 , H01L2924/00014 , H01L2924/01327 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01006 , H01L2224/05552
Abstract: PURPOSE: A semiconductor package prevents defects generated in a reflow process by omitting the reflow process in manufacturing processes. CONSTITUTION: Multiple contact pads (115) are formed on one surface of a semiconductor chip (100). Multiple main bumps (140a) are formed on the contact pads. The main pump includes a first pillar layer (142a) formed on the contact pad and a first solder layer (146a) formed on the first pillar layer. The lower sidewall of the first solder layer is substantially vertical. The upper part of the first solder layer is round. Multiple dummy bumps (140b) are formed on the semiconductor chip around the contact pads.
Abstract translation: 目的：半导体封装通过在制造工艺中省略回流工艺来防止在回流工艺中产生的缺陷。 构成：在半导体芯片（100）的一个表面上形成多个接触焊盘（115）。 多个主凸块（140a）形成在接触垫上。 主泵包括形成在接触焊盘上的第一柱层（142a）和形成在第一柱层上的第一焊料层（146a）。 第一焊料层的下侧壁基本上是垂直的。 第一焊料层的上部是圆形的。 在接触焊盘周围的半导体芯片上形成多个虚设凸块（140b）。
-
公开(公告)号：KR1020110124993A
公开(公告)日：2011-11-18
申请号：KR1020100044498
申请日：2010-05-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/525 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/29 , H01L24/30 , H01L2224/05147 , H01L2224/05166 , H01L2224/05647 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/1412 , H01L2224/29015 , H01L2224/29017 , H01L2224/29019 , H01L2224/29028 , H01L2224/291 , H01L2224/30151 , H01L2224/32106 , H01L2224/32227 , H01L2924/0001 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L21/56 , H01L21/563 , H01L21/568 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
Abstract: PURPOSE: A semiconductor chip, a semiconductor package including the same, and a manufacturing method thereof are provided to improve degree of freedom in a design by rewiring using a bump. CONSTITUTION: A passivation layer(130) is arranged on a semiconductor substrate. A plurality of virtual bumps(120) is arranged on the passivation layer. Penetration bumps are connected to the pad of the semiconductor substrate through the opening of the passivation layer. The size of the penetration bump is equal to the size of the virtual bump. The interval between the penetration bumps is longer than the interval between the virtual bumps.
Abstract translation: 目的：提供一种半导体芯片，包括该半导体芯片的半导体封装及其制造方法，以通过使用凸块重新布线来提高设计中的自由度。 构成：钝化层（130）布置在半导体衬底上。 多个虚拟凸块（120）布置在钝化层上。 穿透凸块通过钝化层的开口连接到半导体衬底的焊盘。 穿透凸块的尺寸等于虚拟凸块的尺寸。 穿透凸块之间的间隔长于虚拟凸块之间的间隔。
-
Patent Agency Ranking
公开(公告)号：KR1020130035619A
公开(公告)日：2013-04-09
申请号：KR1020110100032
申请日：2011-09-30
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13024 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14104 , H01L2224/14515 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2924/3511 , H01L2924/3512 , H01L2924/01022 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01079 , H01L2924/00014 , H01L2924/01047 , H01L2924/01046 , H01L2924/01083 , H01L2924/01051 , H01L2924/014
Abstract: PURPOSE: A method for forming a connection bump of a semiconductor device is provided to prevent a defect due to a flatness problem by positioning the uppermost surfaces of a connection bump and a dummy connection bump with the same level. CONSTITUTION: A photoresist pattern(120) with open patterns is formed. Pillar layers(114) are formed in the open patterns by a first electroplating process. A solder layer(116) is formed on the pillar layers by a second electroplating process. The photoresist pattern is removed. A reflow process is performed on a semiconductor substrate(100) to form a breakdown solder layer and a solder bump.
Abstract translation: 目的：提供一种用于形成半导体器件的连接凸块的方法，通过将连接凸块的最上表面和具有相同电平的虚拟连接凸块定位来防止由于平坦度问题引起的缺陷。 构成：形成具有开放图案的光致抗蚀剂图案（120）。 柱层（114）通过第一电镀工艺以开放图案形成。 通过第二电镀工艺在柱层上形成焊料层（116）。 去除光致抗蚀剂图案。 在半导体衬底（100）上进行回流工艺以形成击穿焊料层和焊料凸块。
-
公开(公告)号：KR1020130004834A
公开(公告)日：2013-01-14
申请号：KR1020110066128
申请日：2011-07-04
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L23/3128 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L2224/02123 , H01L2224/0331 , H01L2224/0332 , H01L2224/0345 , H01L2224/03464 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05022 , H01L2224/05024 , H01L2224/05025 , H01L2224/05026 , H01L2224/05027 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05166 , H01L2224/0519 , H01L2224/05191 , H01L2224/05556 , H01L2224/05558 , H01L2224/05559 , H01L2224/0556 , H01L2224/05562 , H01L2224/05568 , H01L2224/05666 , H01L2224/0569 , H01L2224/05691 , H01L2224/1131 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/13191 , H01L2224/14131 , H01L2224/1416 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/1435 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2224/05552 , H01L2924/00
Abstract: PURPOSE: A semiconductor chip and a flip-chip package including the semiconductor chip are provided to form a buffer made of a metal or an insulating material within a bump structure and to reduce the stress due to the difference of the heat expansion coefficient between the semiconductor chip and a PCB. CONSTITUTION: A body part(110) includes a semiconductor structures and lines. A passivation layer(120) covers the upper surface of the body part and protects the body part. A pad(130) is electrically connected to the lines. A bump structure(180) is formed in the opening part of the passivation layer. The bump structure includes an UBM(Under Bump Metal)(140), a buffer(150) and a bump(160). The buffer is made of a conductive or an insulating material.
Abstract translation: 目的：提供包括半导体芯片的半导体芯片和倒装芯片封装，以在凸块结构内形成由金属或绝缘材料制成的缓冲器，并且减小由于半导体之间的热膨胀系数的差异引起的应力 芯片和PCB。 构成：身体部分（110）包括半导体结构和线。 钝化层（120）覆盖主体部分的上表面并保护身体部位。 衬垫（130）电连接到线路。 在钝化层的开口部分形成凸起结构（180）。 凸块结构包括UBM（低爆破金属）（140），缓冲器（150）和凸块（160）。 缓冲器由导电或绝缘材料制成。
-
公开(公告)号：KR1020120056051A
公开(公告)日：2012-06-01
申请号：KR1020100117565
申请日：2010-11-24
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L21/76804 , H01L21/76885 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/06102 , H01L2224/11462 , H01L2224/11472 , H01L2224/11912 , H01L2224/13021 , H01L2224/13099 , H01L2224/1403 , H01L2224/14515 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014
Abstract: PURPOSE: A semiconductor package and a manufacturing method thereof are provided to reduce the top height difference between a real bump and a dummy bump without adding a special process, thereby improving productivity. CONSTITUTION: A first opening part is formed on a first permeable region(202a) and a semi-permeable region(204). A second opening part is formed on a second permeable region(202b). The first permeable region is arranged to face the lower part of the first opening part. A material film for first and second bumps respectively fills the first and second opening parts. The first and second bumps are formed by performing a reflow process with respect to the material film.
Abstract translation: 目的：提供一种半导体封装及其制造方法，以减少实际凸块和虚设凸块之间的顶部高度差，而不增加特殊工艺，从而提高生产率。 构成：在第一可渗透区域（202a）和半渗透区域（204）上形成第一开口部分。 第二开口部分形成在第二可渗透区域（202b）上。 第一可渗透区域布置成面向第一开口部分的下部。 用于第一和第二凸块的材料膜分别填充第一和第二开口部分。 通过对材料膜进行回流处理来形成第一和第二凸块。
-
公开(公告)号：KR1020110045222A
公开(公告)日：2011-05-04
申请号：KR1020090101683
申请日：2009-10-26
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L24/14 , H01L23/3128 , H01L23/3192 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/05578 , H01L2224/0603 , H01L2224/06515 , H01L2224/13025 , H01L2224/13028 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/1411 , H01L2224/14515 , H01L2224/16145 , H01L2224/16225 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor package and manufacturing method thereof are provided to combine bumps on one printed circuit board pattern, thereby enhancing mechanical and electrical features. CONSTITUTION: A package substrate has a circuit pattern. A semiconductor chip(150) is mounted on the package substrate. The semiconductor chip comprises bumps(130,140) electrically connected to the circuit pattern. The circuit pattern includes a ground pattern(124) and a signal pattern. The signal pattern transfers data between the package substrate and the semiconductor chip.
Abstract translation: 目的：提供半导体封装及其制造方法来组合一个印刷电路板图案上的凸块，从而增强机械和电气特征。 构成：封装衬底具有电路图案。 半导体芯片（150）安装在封装基板上。 半导体芯片包括电连接到电路图案的凸块（130,140）。 电路图案包括接地图案（124）和信号图案。 信号图案在封装基板和半导体芯片之间传送数据。
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.022 seconds)
