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公开(公告)号：KR101695353B1
公开(公告)日：2017-01-11
申请号：KR1020100097418
申请日：2010-10-06
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L25/065
CPC classification number: H01L23/49833 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/06155 , H01L2224/06156 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1147 , H01L2224/13005 , H01L2224/13012 , H01L2224/13016 , H01L2224/13082 , H01L2224/13109 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/13193 , H01L2224/14051 , H01L2224/16145 , H01L2224/16225 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01052 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 범프를통하여회로기판과연결되는반도체패키지가제공된다. 본발명의일 실시예에따른반도체패키지는, 복수개의접속패드가노출되도록형성된반도체칩; 상기각 접속패드상에형성되며, 제1 필라부및 상기제1 필라부상측에형성되는제1 솔더부를포함하는연결용범프들; 상기접속패드주변에서상기접속패드의상부표면보다높은위치에형성되며, 솔더유도부가형성되어있는제2 필라부및 상기제2 필라부상측에형성되는제2 솔더부를포함하는지지용범프들;을포함한다.
Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。
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公开(公告)号：KR1020150143151A
公开(公告)日：2015-12-23
申请号：KR1020140072297
申请日：2014-06-13
Applicant: 삼성전자주식회사
IPC: H01L21/304 , H01L21/66
CPC classification number: H01L22/20 , B24B37/005 , B24B37/042 , B24B49/12 , H01L21/02016 , H01L21/02024 , H01L22/12
Abstract: 본발명의기술적사상에의한웨이퍼의연마방법은, 웨이퍼후면(wafer back side)을폴리싱하는 1차폴리싱단계; 상기웨이퍼후면에존재하는결함을검출하는단계; 상기결함의수준이허용범위밖인지판단하는단계; 상기결함의수준이허용범위밖인경우상기웨이퍼후면을리폴리싱하는 2차폴리싱단계;로이루어진다. 이에따라그라인딩및 폴리싱단계에의해발생하는결함들이허용범위내가되도록재가공될수 있으므로, 웨이퍼후면의균일한품질을확보할수 있어웨이퍼의불량률을효과적으로낮출수 있다.
Abstract translation: 根据本发明的技术思想的用于抛光基板的方法包括：抛光晶片背面的第一抛光步骤; 检测存在于晶片背面的缺陷的步骤; 确定所述缺陷的水平是否在允许范围之外的步骤; 以及第二抛光步骤，当缺陷水平超出允许范围时，重新抛光晶片背面。 因此，通过研磨和抛光步骤产生的缺陷被重新处理以允许缺陷在允许范围内。 因此，可以确保晶片背面的均匀质量，并且可以有效地降低晶片的缺陷率。
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公开(公告)号：KR101782503B1
公开(公告)日：2017-09-28
申请号：KR1020110046940
申请日：2011-05-18
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/13 , H01L24/11 , H01L2224/03 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/1181 , H01L2224/11849 , H01L2224/11902 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/00012 , H01L2924/01047 , H01L2924/01083 , H01L2924/01051 , H01L2924/01029 , H01L2924/01046
Abstract: 솔더층이한쪽방향으로무너지는결함을억제할수 있는반도체소자의범프형성방법에관해개시한다. 이를위해본 발명은최종보호막에의해패드가외부로노출된반도체기판을준비하는단계와, 상기반도체기판전면에시드층을형성하는단계와, 상기패드영역을노출하는포토레지스트패턴을형성하는단계와, 상기포토레지스트에의해노출된영역에 1차전기도금을진행하여필라를형성하는단계와, 상기필라위에 2차전기도금을진행하여솔더층을형성하는단계와, 상기포토레지스트패턴을제거하는단계와, 상기반도체기판에리플로우공정을진행하여솔더가필라의표면을덮는솔더범프를형성하는단계및 상기솔더범프를제외한영역에형성된시드층을제거하는단계를구비하는반도체소자의범프형성방법을제공한다.
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Patent Agency Ranking
公开(公告)号：KR1020140071745A
公开(公告)日：2014-06-12
申请号：KR1020120139679
申请日：2012-12-04
Applicant: 삼성전자주식회사
IPC: H01L21/82
Abstract: Provided is a semiconductor device with improved reliability by preventing a fuse cut by a repair process from being electrically re-connected by electrochemical migration. The semiconductor device includes a substrate, a first fuse pattern and a second fuse pattern which are formed on the substrate and are separated from each other with a first width, a first insulating layer which is formed on the first fuse pattern and the second fuse pattern and includes an opening part which has a second width which is smaller than the first width.
Abstract translation: 提供了一种通过防止由修复过程引起的熔丝断开通过电化学迁移被电连接而提高了可靠性的半导体器件。 半导体器件包括形成在衬底上并以第一宽度彼此分离的衬底，第一熔丝图案和第二熔丝图案，形成在第一熔丝图案上的第一绝缘层和第二熔丝图案 并且包括具有比第一宽度小的第二宽度的开口部。
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公开(公告)号：KR1020140007659A
公开(公告)日：2014-01-20
申请号：KR1020120075039
申请日：2012-07-10
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L23/5226 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76879 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68381 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/11462 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/16225 , H01L2224/19 , H01L2224/24011 , H01L2224/24051 , H01L2224/24147 , H01L2224/32145 , H01L2224/73209 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82106 , H01L2224/83005 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/06517 , H01L2225/06524 , H01L2225/06565 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
Abstract: A multi-chip package according to the present invention comprises a first semiconductor chip, a second semiconductor chip, an insulating film structure, and a plug structure. The first semiconductor chip includes first bonding pads. The second semiconductor chip is located on the first semiconductor chip and includes second bonding pads. The insulating film structure covers the first and second semiconductor chips. The plug structure, which is located inside the insulating film structure and placed apart from sides of the first and second semiconductor chips, is formed by using a plating process and connects the first bonding pad and second bonding pad electrically. Therefore, problems caused by a micro-bump forming process can be completely resolved.
Abstract translation: 根据本发明的多芯片封装包括第一半导体芯片，第二半导体芯片，绝缘膜结构和插头结构。 第一半导体芯片包括第一接合焊盘。 第二半导体芯片位于第一半导体芯片上并且包括第二接合焊盘。 绝缘膜结构覆盖第一和第二半导体芯片。 通过使用电镀工艺形成位于绝缘膜结构内并且与第一和第二半导体芯片的侧面隔开的插塞结构，并且电连接第一焊盘和第二焊盘。 因此，能够完全解决由微凸块形成工序引起的问题。
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公开(公告)号：KR1020120035721A
公开(公告)日：2012-04-16
申请号：KR1020100097418
申请日：2010-10-06
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L25/065
CPC classification number: H01L23/49833 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/06155 , H01L2224/06156 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1147 , H01L2224/13005 , H01L2224/13012 , H01L2224/13016 , H01L2224/13082 , H01L2224/13109 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/13193 , H01L2224/14051 , H01L2224/16145 , H01L2224/16225 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01052 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L21/64 , H01L21/67 , H01L23/48 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor package and a semiconductor package module are provided to arrange a bump with a fine pitch by preventing bridge generation, thereby reducing the size of the semiconductor package. CONSTITUTION: Connection bumps(140a) are formed on each connection pad. The connection bumps include a first pillar part(142a) and a first solder part(144a). Support bumps(140b) are formed on a position near the connection pad with a height higher than the upper surface of the connection pad. The support bumps comprises a second pillar part(142b) and a second solder part(144b). A solder induction part is formed on the second pillar part.
Abstract translation: 目的：提供半导体封装和半导体封装模块以通过防止桥形成而布置具有细间距的凸块，从而减小半导体封装的尺寸。 构成：连接凸块（140a）形成在每个连接垫上。 连接凸块包括第一支柱部分（142a）和第一焊接部分（144a）。 支撑凸块（140b）形成在连接垫附近的位置处，高度高于连接垫的上表面。 支撑凸块包括第二柱部分（142b）和第二焊接部分（144b）。 焊料感应部形成在第二支柱部上。
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公开(公告)号：KR1020130035619A
公开(公告)日：2013-04-09
申请号：KR1020110100032
申请日：2011-09-30
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13024 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14104 , H01L2224/14515 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2924/3511 , H01L2924/3512 , H01L2924/01022 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01079 , H01L2924/00014 , H01L2924/01047 , H01L2924/01046 , H01L2924/01083 , H01L2924/01051 , H01L2924/014
Abstract: PURPOSE: A method for forming a connection bump of a semiconductor device is provided to prevent a defect due to a flatness problem by positioning the uppermost surfaces of a connection bump and a dummy connection bump with the same level. CONSTITUTION: A photoresist pattern(120) with open patterns is formed. Pillar layers(114) are formed in the open patterns by a first electroplating process. A solder layer(116) is formed on the pillar layers by a second electroplating process. The photoresist pattern is removed. A reflow process is performed on a semiconductor substrate(100) to form a breakdown solder layer and a solder bump.
Abstract translation: 目的：提供一种用于形成半导体器件的连接凸块的方法，通过将连接凸块的最上表面和具有相同电平的虚拟连接凸块定位来防止由于平坦度问题引起的缺陷。 构成：形成具有开放图案的光致抗蚀剂图案（120）。 柱层（114）通过第一电镀工艺以开放图案形成。 通过第二电镀工艺在柱层上形成焊料层（116）。 去除光致抗蚀剂图案。 在半导体衬底（100）上进行回流工艺以形成击穿焊料层和焊料凸块。
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公开(公告)号：KR1020130004834A
公开(公告)日：2013-01-14
申请号：KR1020110066128
申请日：2011-07-04
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L23/3128 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/81 , H01L2224/02123 , H01L2224/0331 , H01L2224/0332 , H01L2224/0345 , H01L2224/03464 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05022 , H01L2224/05024 , H01L2224/05025 , H01L2224/05026 , H01L2224/05027 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05166 , H01L2224/0519 , H01L2224/05191 , H01L2224/05556 , H01L2224/05558 , H01L2224/05559 , H01L2224/0556 , H01L2224/05562 , H01L2224/05568 , H01L2224/05666 , H01L2224/0569 , H01L2224/05691 , H01L2224/1131 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/13191 , H01L2224/14131 , H01L2224/1416 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/1435 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2224/05552 , H01L2924/00
Abstract: PURPOSE: A semiconductor chip and a flip-chip package including the semiconductor chip are provided to form a buffer made of a metal or an insulating material within a bump structure and to reduce the stress due to the difference of the heat expansion coefficient between the semiconductor chip and a PCB. CONSTITUTION: A body part(110) includes a semiconductor structures and lines. A passivation layer(120) covers the upper surface of the body part and protects the body part. A pad(130) is electrically connected to the lines. A bump structure(180) is formed in the opening part of the passivation layer. The bump structure includes an UBM(Under Bump Metal)(140), a buffer(150) and a bump(160). The buffer is made of a conductive or an insulating material.
Abstract translation: 目的：提供包括半导体芯片的半导体芯片和倒装芯片封装，以在凸块结构内形成由金属或绝缘材料制成的缓冲器，并且减小由于半导体之间的热膨胀系数的差异引起的应力 芯片和PCB。 构成：身体部分（110）包括半导体结构和线。 钝化层（120）覆盖主体部分的上表面并保护身体部位。 衬垫（130）电连接到线路。 在钝化层的开口部分形成凸起结构（180）。 凸块结构包括UBM（低爆破金属）（140），缓冲器（150）和凸块（160）。 缓冲器由导电或绝缘材料制成。
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