公开(公告)号：KR1020080070457A

公开(公告)日：2008-07-30

申请号：KR1020070008602

申请日：2007-01-26

Applicant: 삼성전자주식회사

Inventor： 최신일 ,  김상갑 ,  오민석 ,  진홍기 ,  정유광 ,  최승하

IPC: H04R1/24 ,  H05H1/30 ,  H05H1/34

CPC classification number: H01J37/32532 ,  H01J37/32082 ,  H01J37/32633 ,  H05H1/46

Abstract: A plasma generation apparatus is provided to improve uniformity of a surface processing of an object by ejecting plasma into an ejection hole which is arranged uniformly. A plasma generation apparatus includes a power terminal(20), a first ground terminal(30), a first dielectric body(50), a second ground terminal(40), and an ejection hole(70). A high frequency voltage is applied to the power terminal. The first ground terminal is arranged to be opposite to the power terminal, and is grounded. The first dielectric body is located between the power terminal and the first ground terminal, and electrically insulates the power terminal from the first ground terminal. The second ground terminal is arranged to be apart from a lower part of the first ground terminal and the power terminal. The second ground terminal is grounded. The ejection hole is formed to be penetrated by the second ground terminal.

Abstract translation: 提供了一种等离子体产生装置，以通过将等离子体喷射到均匀排列的喷射孔中来提高物体的表面处理的均匀性。 等离子体产生装置包括电源端子（20），第一接地端子（30），第一电介质体（50），第二接地端子（40）和喷射孔（70）。 向电源端子施加高频电压。 第一接地端子被布置为与电源端子相对，并且接地。 第一绝缘体位于电源端子与第一接地端子之间，并将电源端子与第一接地端子电绝缘。 第二接地端子被布置成与第一接地端子和电源端子的下部分开。 第二个接地端接地。 喷射孔形成为被第二接地端子穿透。

公开(公告)号：KR1020080035150A

公开(公告)日：2008-04-23

申请号：KR1020060101428

申请日：2006-10-18

Applicant: 삼성전자주식회사

Inventor： 최승하 ,  김상갑 ,  오민석 ,  최신일 ,  김대옥 ,  진홍기 ,  정영호 ,  정유광

IPC: H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L21/02068 ,  H01L29/66765

Abstract: A method for fabricating a TFT substrate is provided to avoid a skew phenomenon of a source/drain electrode by forming the source/drain electrode by a dry etch process. A gate interconnection, a gate insulation layer, an active layer, a conductive layer for a data interconnection, and a photoresist pattern composed of first and second regions are sequentially formed on an insulation substrate(10). By using the photoresist pattern as an etch mask, the conductive layer for the data interconnection is etched to form a conductive pattern for a source/drain electrode(65,66) and a data line(62). By using the photoresist pattern as an etch mask, the active layer is etched to form an active layer pattern. The second region of the photoresist pattern is removed. By employing etch gas and using the photoresist pattern as an etch mask, the conductive layer pattern for the source/drain electrode under the second region is dry-etched. A part of the active layer pattern is etched by using the photoresist pattern as an etch mask. Reaction byproducts of the conductive layer pattern for the source/drain electrode are physically removed by a reaction byproducts removing agent so that external force is applied to the etch gas and the reaction byproducts. The photoresist pattern is stripped, and a passivation layer(70) and a pixel electrode are formed.

Abstract translation: 提供一种用于制造TFT基板的方法，以通过干法蚀刻工艺形成源/漏电极来避免源极/漏极的偏斜现象。 在绝缘基板（10）上依次形成栅极互连，栅极绝缘层，有源层，数据互连用导电层和由第一和第二区域构成的光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，蚀刻用于数据互连的导电层以形成用于源极/漏极（65,66）和数据线（62）的导电图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，有源层被蚀刻以形成有源层图案。 除去光致抗蚀剂图案的第二区域。 通过使用蚀刻气体并使用光致抗蚀剂图案作为蚀刻掩模，在第二区域下的源极/漏极电极的导电层图案被干蚀刻。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻有源层图案的一部分。 用于源/漏电极的导电层图案的反应副产物通过反应副产物去除剂物理去除，使得外力施加到蚀刻气体和反应副产物。 剥离光致抗蚀剂图案，形成钝化层（70）和像素电极。

公开(公告)号：KR1020100062544A

公开(公告)日：2010-06-10

申请号：KR1020080121228

申请日：2008-12-02

Applicant: 삼성전자주식회사

Inventor： 최승하 ,  김상갑 ,  신봉규 ,  임상욱 ,  주진호 ,  양성훈 ,  황보상우 ,  최재호 ,  이기엽 ,  여윤종 ,  최신일 ,  양동주 ,  진홍기 ,  정유광

IPC: G02F1/136 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/7869 ,  H01L21/311 ,  H01L27/1214

Abstract: PURPOSE: A thin film transistor substrate is provided to prevent the film characteristics of insulation and protection films from being lowered by adding a hydrogen gas to a deposition process. CONSTITUTION: A gate line is formed on an insulating substrate(10), and a gate insulating layer(30) is formed on the gate line. A data line is formed on the gate insulation film, and a protection film(60) is formed on the data line. A contact hole(65) is formed by etching at least one of the gate insulation film and the protection film.

Abstract translation: 目的：提供薄膜晶体管基板，以通过向沉积工艺添加氢气来防止绝缘和保护膜的膜特性降低。 构成：在绝缘基板（10）上形成栅极线，栅极线上形成有栅极绝缘层（30）。 在栅极绝缘膜上形成数据线，在数据线上形成保护膜（60）。 通过蚀刻栅极绝缘膜和保护膜中的至少一个来形成接触孔（65）。

公开(公告)号：KR1020080057779A

公开(公告)日：2008-06-25

申请号：KR1020060131470

申请日：2006-12-21

Applicant: 삼성전자주식회사

Inventor： 김상갑 ,  오민석 ,  정유광 ,  김시열 ,  최신일 ,  최승하

IPC: G02F1/136

CPC classification number: G02F1/13458 ,  G02F2201/123 ,  H01L21/0273 ,  H01L29/786

Abstract: A method for manufacturing a TFT(Thin Film Transistor) substrate is provided to pattern a data metal film through a wet etching process and a dry etching process. A gate insulating film and an active layer(140) are successively formed on a substrate(110) in which a gate wire is formed. A data metal film(150) in which the first to the third metal layers(151~153) are continuously laminated is formed on the active layer. The first photoresist pattern(160) in which a channel forming region has a thickness which is relatively thinner than other regions is formed on the data metal layer. The data metal layer and the active layer are etched by using the first photoresist pattern. The first photoresist pattern is etched, and the second photoresist pattern in which the channel forming region is opened is formed. A primary dry etching of the third metal layer of the channel forming region is performed by using the second photoresist pattern. Secondary dry etching of the second metal layer is performed, and tertiary dry etching of the first metal layer is performed by using the second photoresist pattern.

Abstract translation: 提供一种用于制造TFT（薄膜晶体管）基板的方法，以通过湿蚀刻工艺和干蚀刻工艺对数据金属膜进行图案化。 栅极绝缘膜和有源层（140）依次形成在其上形成有栅极线的基板（110）上。 在有源层上形成连续层叠有第一〜第三金属层（151〜153）的数据金属膜（150）。 在数据金属层上形成第一光致抗蚀剂图案（160），其中沟道形成区域的厚度比其它区域薄。 通过使用第一光致抗蚀剂图案蚀刻数据金属层和有源层。 蚀刻第一光致抗蚀剂图案，形成其中打开通道形成区域的第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案来进行沟道形成区域的第三金属层的主干蚀刻。 执行第二金属层的二次干法蚀刻，并且通过使用第二光致抗蚀剂图案来执行第一金属层的三次干蚀刻。

公开(公告)号：KR1020100067413A

公开(公告)日：2010-06-21

申请号：KR1020080125975

申请日：2008-12-11

Applicant: 삼성전자주식회사 ,  주식회사 플라즈마트

Inventor： 최신일 ,  진홍기 ,  김상갑 ,  이기엽 ,  양동주 ,  정유광 ,  최승하 ,  여윤종 ,  박지영 ,  김형준 ,  이상선

IPC: H01L21/66 ,  H01L21/3065 ,  H01L21/205

CPC classification number: G01R33/12

Abstract: PURPOSE: A contactless plasma monitoring apparatus, a plasma processing apparatus and a contactless plasma monitoring method are provided to maintain a plasma state in a processing chamber with proper condition to a plasma process by controlling a voltage provided to the processing chamber in a real time. CONSTITUTION: A processing chamber(100) supplies a reaction space(150) in which the process is implemented using a plasma(140). The processing chamber includes an upper electrode(110) and a lower electrode(120). A power supply unit(300) supplies the power supply to the processing chamber. The power supply unit includes a power generating unit(320) with generating the power supply to the processing chamber and a matching box(310). The matching box controls the intensity of the generated power source and supplies to the processing chamber. A power supply wiring(200) connects the processing chamber with the power supply unit.

Abstract translation: 目的：提供一种非接触式等离子体监测装置，等离子体处理装置和非接触式等离子体监测方法，以通过实时控制提供给处理室的电压，将处于等离子体状态的等离子体状态保持在等离子体处理的适当条件。 构成：处理室（100）提供使用等离子体（140）实现该过程的反应空间（150）。 处理室包括上电极（110）和下电极（120）。 电源单元（300）将电源供应到处理室。 电源单元包括产生对处理室的电源的发电单元（320）和匹配箱（310）。 匹配箱控制所产生的电源的强度并供应给处理室。 电源线（200）将处理室与电源单元连接。

公开(公告)号：KR1020090080786A

公开(公告)日：2009-07-27

申请号：KR1020080006751

申请日：2008-01-22

Applicant: 삼성전자주식회사

Inventor： 김상갑 ,  오민석 ,  정유광 ,  박홍식 ,  김시열 ,  김장수 ,  최신일

IPC: H01L29/786

CPC classification number: G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L21/02068 ,  H01L27/1214

Abstract: A manufacturing method of an array substrate is provided to minimize damage to a fine pattern. A gate line(122) and a gate electrode(124) are formed on a base substrate(110). A source metal layer(150) is formed on the base substrate on which the gate line and the gate electrode are formed. A data line(155), a source electrode(157), and a drain electrode(158) are formed by etching the source metal layer. The data line intersects with the gate line. The source electrode is connected to the data line. The drain electrode is isolated from the source electrode. An additive gas is provided on the base substrate on which the drain electrode is formed. An etching component of an etching gas reacts to the source metal layer. A by-product formed on each side wall of the data line, the source electrode, and the drain electrode is removed. A pixel electrode is contacted with the drain electrode.

Abstract translation: 提供阵列基板的制造方法以最小化对精细图案的损伤。 栅基线（122）和栅电极（124）形成在基底（110）上。 源极金属层（150）形成在其上形成有栅极线和栅电极的基底基板上。 通过蚀刻源极金属层形成数据线（155），源极（157）和漏极（158）。 数据线与栅极线相交。 源电极连接到数据线。 漏电极与源电极隔离。 在形成有漏电极的基底基板上设置有添加气体。 蚀刻气体的蚀刻成分与源极金属层反应。 除去形成在数据线，源电极和漏电极的每个侧壁上的副产物。 像素电极与漏电极接触。

公开(公告)号：KR1020090076046A

公开(公告)日：2009-07-13

申请号：KR1020080001784

申请日：2008-01-07

Applicant: 삼성전자주식회사

Inventor： 최승하 ,  오민석 ,  정유광 ,  진홍기 ,  최신일 ,  김상갑 ,  윤갑수 ,  정두희

IPC: G02F1/136

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1288

Abstract: A liquid crystal display and a manufacturing method thereof are provided to reduce line resistance of the liquid crystal display, thereby improving reliability. A gate electrode(122) is formed on an insulating substrate(110). An active layer(140) is formed on the gate electrode. An organic substance layer(150) is formed on the active layer. The organic substance layer comprises the first hole exposing a source area and the second hole exposing a drain area. A source electrode(192) is charged in the first hole. A drain electrode(194) is charged in the second hole.

Abstract translation: 提供液晶显示器及其制造方法以降低液晶显示器的线路电阻，从而提高可靠性。 在绝缘基板（110）上形成栅电极（122）。 在栅电极上形成有源层（140）。 在有源层上形成有机物质层（150）。 有机物质层包括暴露源区域的第一孔和暴露漏极区域的第二孔。 源电极（192）在第一孔中充电。 漏电极（194）装入第二孔。