公开(公告)号：KR1020080070457A

公开(公告)日：2008-07-30

申请号：KR1020070008602

申请日：2007-01-26

Applicant: 삼성전자주식회사

Inventor： 최신일 ,  김상갑 ,  오민석 ,  진홍기 ,  정유광 ,  최승하

IPC: H04R1/24 ,  H05H1/30 ,  H05H1/34

CPC classification number: H01J37/32532 ,  H01J37/32082 ,  H01J37/32633 ,  H05H1/46

Abstract: A plasma generation apparatus is provided to improve uniformity of a surface processing of an object by ejecting plasma into an ejection hole which is arranged uniformly. A plasma generation apparatus includes a power terminal(20), a first ground terminal(30), a first dielectric body(50), a second ground terminal(40), and an ejection hole(70). A high frequency voltage is applied to the power terminal. The first ground terminal is arranged to be opposite to the power terminal, and is grounded. The first dielectric body is located between the power terminal and the first ground terminal, and electrically insulates the power terminal from the first ground terminal. The second ground terminal is arranged to be apart from a lower part of the first ground terminal and the power terminal. The second ground terminal is grounded. The ejection hole is formed to be penetrated by the second ground terminal.

Abstract translation: 提供了一种等离子体产生装置，以通过将等离子体喷射到均匀排列的喷射孔中来提高物体的表面处理的均匀性。 等离子体产生装置包括电源端子（20），第一接地端子（30），第一电介质体（50），第二接地端子（40）和喷射孔（70）。 向电源端子施加高频电压。 第一接地端子被布置为与电源端子相对，并且接地。 第一绝缘体位于电源端子与第一接地端子之间，并将电源端子与第一接地端子电绝缘。 第二接地端子被布置成与第一接地端子和电源端子的下部分开。 第二个接地端接地。 喷射孔形成为被第二接地端子穿透。

公开(公告)号：KR1020080035150A

公开(公告)日：2008-04-23

申请号：KR1020060101428

申请日：2006-10-18

Applicant: 삼성전자주식회사

Inventor： 최승하 ,  김상갑 ,  오민석 ,  최신일 ,  김대옥 ,  진홍기 ,  정영호 ,  정유광

IPC: H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L21/02068 ,  H01L29/66765

Abstract: A method for fabricating a TFT substrate is provided to avoid a skew phenomenon of a source/drain electrode by forming the source/drain electrode by a dry etch process. A gate interconnection, a gate insulation layer, an active layer, a conductive layer for a data interconnection, and a photoresist pattern composed of first and second regions are sequentially formed on an insulation substrate(10). By using the photoresist pattern as an etch mask, the conductive layer for the data interconnection is etched to form a conductive pattern for a source/drain electrode(65,66) and a data line(62). By using the photoresist pattern as an etch mask, the active layer is etched to form an active layer pattern. The second region of the photoresist pattern is removed. By employing etch gas and using the photoresist pattern as an etch mask, the conductive layer pattern for the source/drain electrode under the second region is dry-etched. A part of the active layer pattern is etched by using the photoresist pattern as an etch mask. Reaction byproducts of the conductive layer pattern for the source/drain electrode are physically removed by a reaction byproducts removing agent so that external force is applied to the etch gas and the reaction byproducts. The photoresist pattern is stripped, and a passivation layer(70) and a pixel electrode are formed.

Abstract translation: 提供一种用于制造TFT基板的方法，以通过干法蚀刻工艺形成源/漏电极来避免源极/漏极的偏斜现象。 在绝缘基板（10）上依次形成栅极互连，栅极绝缘层，有源层，数据互连用导电层和由第一和第二区域构成的光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，蚀刻用于数据互连的导电层以形成用于源极/漏极（65,66）和数据线（62）的导电图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，有源层被蚀刻以形成有源层图案。 除去光致抗蚀剂图案的第二区域。 通过使用蚀刻气体并使用光致抗蚀剂图案作为蚀刻掩模，在第二区域下的源极/漏极电极的导电层图案被干蚀刻。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻有源层图案的一部分。 用于源/漏电极的导电层图案的反应副产物通过反应副产物去除剂物理去除，使得外力施加到蚀刻气体和反应副产物。 剥离光致抗蚀剂图案，形成钝化层（70）和像素电极。

公开(公告)号：KR1020080008734A

公开(公告)日：2008-01-24

申请号：KR1020060068334

申请日：2006-07-21

Applicant: 삼성전자주식회사

Inventor： 정창오 ,  김상갑 ,  석준형 ,  김홍균 ,  황인선 ,  오민석 ,  진홍기 ,  정유광 ,  최승하 ,  이희국 ,  김시열

IPC: G02F1/1343 ,  G02F1/1335

CPC classification number: G02F1/133528 ,  G02F1/134336 ,  G02F2001/133548 ,  H01L27/12

Abstract: A display panel, a display device and a manufacturing method thereof are provided to use an electrode of the display device as a polarizing panel, thereby removing the polarizing panel arranged at the rear of the display panel and simplifying the processes. A gate line is formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate line. A data line is crossed with the gate line and includes a source electrode. A drain electrode(175) is located oppositely to the source electrode. Plural line patterns(193) are electrically connected with the drain electrode and polarizes the incidence light beam. The distance of line patterns is below 200 nanometer. The width of the line pattern is below 100 nanometer. An alignment layer is formed on the electrode. The electrode includes at least one among Al, Ag, Cu, Mo, Cr, Ta, Ti or alloy thereof. The gate insulating layer includes an opened pixel area.

Abstract translation: 提供显示面板，显示装置及其制造方法以使用显示装置的电极作为偏振面板，从而去除布置在显示面板后部的偏振片，并简化了工艺。 在基板上形成栅极线。 栅极绝缘层形成在衬底上以覆盖栅极线。 数据线与栅极线交叉并且包括源电极。 漏电极（175）位于与源电极相对的位置。 多个线图案（193）与漏电极电连接并使入射光束偏振。 线条的距离低于200纳米。 线图案的宽度低于100纳米。 在电极上形成取向层。 电极包括Al，Ag，Cu，Mo，Cr，Ta，Ti或其合金中的至少一种。 栅极绝缘层包括开放的像素区域。

公开(公告)号：KR1020070055053A

公开(公告)日：2007-05-30

申请号：KR1020050113322

申请日：2005-11-25

Applicant: 삼성전자주식회사

Inventor： 김상갑 ,  김시열 ,  오민석 ,  진홍기 ,  최승하 ,  정유광

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  G02F2201/123

Abstract: 표시 화면의 잔상을 개선하기 위한 표시 기판이 개시된다. 표시 기판은 제1 금속패턴으로 형성된 게이트 배선으로부터 연장된 게이트 전극과, 제2 금속패턴으로 형성된 소스 배선으로부터 연장된 소스 전극과, 제2 금속패턴으로 형성되고 소스 전극과 일정한 이격 거리를 갖는 드레인 전극과, 드레인 전극과 연결되어 드레인 전극과 화소 전극을 전기적으로 연결시키는 연결 패턴 및 연결 패턴의 하부에 형성되어 상기 연결 패턴을 커버하는 실딩 패턴을 포함한다. 실딩 패턴이 연결 패턴으로 조사되는 배면광을 차단시키므로 누설광 및 광 누설 전류의 발생이 감소된다. 이에 따라, 광 누설 전류로 인한 표시 화면의 잔상 발생을 개선할 수 있다.
광 누설 전류, 실딩 패턴, 4매 공정, 알루미늄 배선

公开(公告)号：KR1020070040145A

公开(公告)日：2007-04-16

申请号：KR1020050095525

申请日：2005-10-11

Applicant: 삼성전자주식회사

Inventor： 진홍기 ,  김상갑 ,  황태형 ,  오민석 ,  정유광 ,  최승하

IPC: G02F1/136

CPC classification number: H01L27/1222 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/06 ,  H01L29/66765 ,  H01L29/78603

Abstract: A flexible display panel according to an embodiment of the present invention includes a flexible substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the substrate, a semiconductor layer formed on the gate insulating layer and disposed substantially on the entire gate electrode, a source electrode and a drain electrode formed on the semiconductor layer, and a pixel electrode connected to the drain electrode. The patterning of the semiconductor layer to form a second semiconductor member may include coating a photoresist film on a first semiconductor member, exposing the photoresist film to light from a back of the substrate, wherein the gate electrode is used as a light blocking mask, developing the exposed photoresist film to form a photoresist pattern having the same planar size as the gate electrode, and etching the semiconductor layer using the photoresist pattern as an etching mask.

公开(公告)号：KR1020100062544A

公开(公告)日：2010-06-10

申请号：KR1020080121228

申请日：2008-12-02

Applicant: 삼성전자주식회사

Inventor： 최승하 ,  김상갑 ,  신봉규 ,  임상욱 ,  주진호 ,  양성훈 ,  황보상우 ,  최재호 ,  이기엽 ,  여윤종 ,  최신일 ,  양동주 ,  진홍기 ,  정유광

IPC: G02F1/136 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/7869 ,  H01L21/311 ,  H01L27/1214

Abstract: PURPOSE: A thin film transistor substrate is provided to prevent the film characteristics of insulation and protection films from being lowered by adding a hydrogen gas to a deposition process. CONSTITUTION: A gate line is formed on an insulating substrate(10), and a gate insulating layer(30) is formed on the gate line. A data line is formed on the gate insulation film, and a protection film(60) is formed on the data line. A contact hole(65) is formed by etching at least one of the gate insulation film and the protection film.

Abstract translation: 目的：提供薄膜晶体管基板，以通过向沉积工艺添加氢气来防止绝缘和保护膜的膜特性降低。 构成：在绝缘基板（10）上形成栅极线，栅极线上形成有栅极绝缘层（30）。 在栅极绝缘膜上形成数据线，在数据线上形成保护膜（60）。 通过蚀刻栅极绝缘膜和保护膜中的至少一个来形成接触孔（65）。

公开(公告)号：KR1020080057779A

公开(公告)日：2008-06-25

申请号：KR1020060131470

申请日：2006-12-21

Applicant: 삼성전자주식회사

Inventor： 김상갑 ,  오민석 ,  정유광 ,  김시열 ,  최신일 ,  최승하

IPC: G02F1/136

CPC classification number: G02F1/13458 ,  G02F2201/123 ,  H01L21/0273 ,  H01L29/786

Abstract: A method for manufacturing a TFT(Thin Film Transistor) substrate is provided to pattern a data metal film through a wet etching process and a dry etching process. A gate insulating film and an active layer(140) are successively formed on a substrate(110) in which a gate wire is formed. A data metal film(150) in which the first to the third metal layers(151~153) are continuously laminated is formed on the active layer. The first photoresist pattern(160) in which a channel forming region has a thickness which is relatively thinner than other regions is formed on the data metal layer. The data metal layer and the active layer are etched by using the first photoresist pattern. The first photoresist pattern is etched, and the second photoresist pattern in which the channel forming region is opened is formed. A primary dry etching of the third metal layer of the channel forming region is performed by using the second photoresist pattern. Secondary dry etching of the second metal layer is performed, and tertiary dry etching of the first metal layer is performed by using the second photoresist pattern.

Abstract translation: 提供一种用于制造TFT（薄膜晶体管）基板的方法，以通过湿蚀刻工艺和干蚀刻工艺对数据金属膜进行图案化。 栅极绝缘膜和有源层（140）依次形成在其上形成有栅极线的基板（110）上。 在有源层上形成连续层叠有第一〜第三金属层（151〜153）的数据金属膜（150）。 在数据金属层上形成第一光致抗蚀剂图案（160），其中沟道形成区域的厚度比其它区域薄。 通过使用第一光致抗蚀剂图案蚀刻数据金属层和有源层。 蚀刻第一光致抗蚀剂图案，形成其中打开通道形成区域的第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案来进行沟道形成区域的第三金属层的主干蚀刻。 执行第二金属层的二次干法蚀刻，并且通过使用第二光致抗蚀剂图案来执行第一金属层的三次干蚀刻。

公开(公告)号：KR1020080040442A

公开(公告)日：2008-05-08

申请号：KR1020060108416

申请日：2006-11-03

Applicant: 삼성전자주식회사

Inventor： 오민석 ,  김상갑 ,  진홍기 ,  정유광 ,  최승하 ,  김기현 ,  송인호

IPC: H01L29/786 ,  H01L21/304

CPC classification number: H01L22/12 ,  H01L27/1288 ,  H01L2924/0002 ,  H01L21/02068 ,  H01L27/1214 ,  H01L2924/00

Abstract: A method for manufacturing a thin film transistor display panel and a manufacturing system using the same are provided to reduce the error rate of a liquid crystal display device by preventing generation of corrosive foreign materials in a manufacturing process. A deposition process is performed to deposit a metallic thin film on a display panel(S111). An insulating substrate deposited with a metallic thin film is provided into an etch unit to perform a dry-etch process for forming a predetermined circuit pattern(S112). The insulating substrate is provided into a standby unit to perform a cleaning and standby process(S113). A preliminary cleaning process is performed(S114). A determination process is performed to determine the state of a cleaning operation(S115). A main cleaning process is performed(S116).

Abstract translation: 提供一种制造薄膜晶体管显示面板的方法和使用该方法的制造系统，以通过在制造过程中防止产生腐蚀性异物来降低液晶显示装置的误差率。 进行沉积处理以在显示面板上沉积金属薄膜（S111）。 将沉积有金属薄膜的绝缘衬底提供到蚀刻单元中以执行用于形成预定电路图案的干法蚀刻工艺（S112）。 将绝缘基板设置在待机单元中以执行清洁和待机处理（S113）。 进行初步清洗处理（S114）。 执行确定处理以确定清洁操作的状态（S115）。 执行主要清洁处理（S116）。

公开(公告)号：KR1020080024763A

公开(公告)日：2008-03-19

申请号：KR1020060089312

申请日：2006-09-14

Applicant: 삼성전자주식회사

Inventor： 오민석 ,  김상갑 ,  박홍식 ,  진홍기 ,  정유광 ,  최승하

IPC: G02F1/136 ,  H01L29/786

CPC classification number: G02F1/136286 ,  H01L29/458

Abstract: A thin film transistor display panel and its fabrication method are provided to obtain low resistance of wirings and the reliability. A gate line(121) is formed on an insulation substrate. A gate insulating layer is formed on the gate line. A semiconductor(151) is formed on the gate insulating layer. Ohmic contacts are formed on the semiconductor. A data line(171) is formed on the ohmic contacts and includes a source electrode(173). A drain electrode faces the source electrode. A pixel electrode is connected with the drain electrode. At least one of the data line and the drain electrode includes the first contact layer, the second contact layer including a conductive oxide, and a conductive layer containing silver or a silver alloy.

Abstract translation: 提供一种薄膜晶体管显示面板及其制造方法，以获得较低的布线电阻和可靠性。 在绝缘基板上形成栅极线（121）。 在栅极线上形成栅极绝缘层。 在栅极绝缘层上形成半导体（151）。 在半导体上形成欧姆接触。 数据线（171）形成在欧姆接触上，并包括源电极（173）。 漏电极面对源电极。 像素电极与漏电极连接。 数据线和漏电极中的至少一个包括第一接触层，第二接触层包括导电氧化物，以及包含银或银合金的导电层。

公开(公告)号：KR1020100067413A

公开(公告)日：2010-06-21

申请号：KR1020080125975

申请日：2008-12-11

Applicant: 삼성전자주식회사 ,  주식회사 플라즈마트

Inventor： 최신일 ,  진홍기 ,  김상갑 ,  이기엽 ,  양동주 ,  정유광 ,  최승하 ,  여윤종 ,  박지영 ,  김형준 ,  이상선

IPC: H01L21/66 ,  H01L21/3065 ,  H01L21/205

CPC classification number: G01R33/12

Abstract: PURPOSE: A contactless plasma monitoring apparatus, a plasma processing apparatus and a contactless plasma monitoring method are provided to maintain a plasma state in a processing chamber with proper condition to a plasma process by controlling a voltage provided to the processing chamber in a real time. CONSTITUTION: A processing chamber(100) supplies a reaction space(150) in which the process is implemented using a plasma(140). The processing chamber includes an upper electrode(110) and a lower electrode(120). A power supply unit(300) supplies the power supply to the processing chamber. The power supply unit includes a power generating unit(320) with generating the power supply to the processing chamber and a matching box(310). The matching box controls the intensity of the generated power source and supplies to the processing chamber. A power supply wiring(200) connects the processing chamber with the power supply unit.

Abstract translation: 目的：提供一种非接触式等离子体监测装置，等离子体处理装置和非接触式等离子体监测方法，以通过实时控制提供给处理室的电压，将处于等离子体状态的等离子体状态保持在等离子体处理的适当条件。 构成：处理室（100）提供使用等离子体（140）实现该过程的反应空间（150）。 处理室包括上电极（110）和下电极（120）。 电源单元（300）将电源供应到处理室。 电源单元包括产生对处理室的电源的发电单元（320）和匹配箱（310）。 匹配箱控制所产生的电源的强度并供应给处理室。 电源线（200）将处理室与电源单元连接。