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公开(公告)号：KR1020150063616A
公开(公告)日：2015-06-10
申请号：KR1020130147480
申请日：2013-11-29
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C17/16 , G11C17/18 , G11C29/027 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C2029/4402
Abstract: 본발명은반도체메모리장치의테스트방법및 그러한테스트를수행하는반도체메모리시스템에관한것이다. 본발명에의한메모리셀 어레이및 안티퓨즈어레이를포함하는반도체메모리장치의테스트방법은상기메모리셀 어레이에포함된페일셀들을검출하는단계, 상기검출된페일셀들에대응되는페일어드레스를판별하는단계, 상기판별된페일어드레스를상기메모리셀 어레이에포함된페일어드레스메모리영역에저장하는단계및 상기페일어드레스메모리영역에저장된페일어드레스를리드하여상기안티퓨즈어레이에프로그램하는단계를포함한다. 본발명에의한반도체메모리장치테스트방법및 반도체메모리시스템에의하면, 테스트동작이어드레스를저장하기위한추가적인메모리없이수행될수 있으므로반도체메모리장치및 테스트회로가작은면적으로구현될수 있다.
Abstract translation: 本发明涉及一种测试半导体存储器件和执行该测试的半导体存储器系统的方法。 根据本发明的包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括以下步骤：检测包括在存储单元阵列中的故障单元; 确定对应于检测到的故障小区的故障地址; 将所确定的故障地址存储在所述存储单元阵列中包括的故障地址存储器区域中; 并通过读取存储在故障地址存储器区域中的故障地址来编程反熔丝阵列。 通过根据本发明的用于测试半导体存储器件和半导体存储器系统的方法，半导体存储器件和测试电路通过执行测试操作而以小的面积实现，而没有用于存储地址的附加存储器。
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公开(公告)号：KR101975528B1
公开(公告)日：2019-05-07
申请号：KR1020120077969
申请日：2012-07-17
Applicant: 삼성전자주식회사
IPC: G11C8/00 , G11C11/408 , G11C11/413
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公开(公告)号：KR101799439B1
公开(公告)日：2017-11-20
申请号：KR1020130027867
申请日：2013-03-15
Applicant: 삼성전자주식회사
IPC: G06F12/06
Abstract: 메모리시스템은메모리모듈및 메모리컨트롤러를포함한다. 메모리모듈은불량이발생한배드페이지를정상페이지로리플레이스한다. 메모리모듈은베드페이지의개수를기초로덴시티(density) 정보를생성한다. 메모리컨트롤러는메모리모듈로부터수신한덴시티정보를기초로피지컬어드레스를메모리모듈의디램어드레스로연속적으로맵핑한다.
Abstract translation: 存储器系统包括存储器模块和存储器控制器。 内存模块用普通页面替换有缺陷的坏页面。 存储器模块基于床单页数生成密度信息。 存储器控制器基于从存储器模块接收的密集信息连续地将物理地址映射到存储器模块的DRAM地址。
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Patent Agency Ranking
公开(公告)号：KR1020150020477A
公开(公告)日：2015-02-26
申请号：KR1020130097278
申请日：2013-08-16
Applicant: 삼성전자주식회사
IPC: G11C8/12 , G11C7/12 , G11C11/4091
CPC classification number: G11C8/08 , G11C7/1042 , G11C7/12 , G11C8/10
Abstract: 메모리 장치, 이를 포함하는 메모리 시스템 및 그 동작 방법이 제공된다. 상기 메모리 장치는 제1 및 제2 서브뱅크를 포함하는 적어도 하나의 메모리 뱅크, ACT 커맨드에 응답하여, 상기 제1 및 제2 서브뱅크 중 선택된 하나의 서브뱅크의 로우를 활성화하는 로우 디코더, 및 PRE 커맨드에 응답하여, 상기 제1 및 제2 서브뱅크에 대하여 각각 프리차지를 수행하는 제1 및 제2 센스 앰프를 포함하되, 상기 제1 서브뱅크의 로우를 활성화하기 위한 ACT 커맨드에 응답하여, 상기 제2 센스 앰프가 상기 제2 서브뱅크에 대하여 프리차지를 수행한다.
Abstract translation: 提供了能够支持子存储体级的并行操作的存储器件，包括该存储器件的存储器系统及其操作方法。 所述存储装置包括至少一个包括第一子库和第二子库的存储体，行解码器，其响应于ACT命令来激活从所述第一子库和所述第二子库中选择的一个子库的行，以及第一和 响应于PRE命令对第一和第二子存储体进行预充电的第二读出放大器。 第二读出放大器响应于ACT命令来预充电第二子存储体以激活第一子存储体的行。
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公开(公告)号：KR1020140123203A
公开(公告)日：2014-10-22
申请号：KR1020130040123
申请日：2013-04-11
Applicant: 삼성전자주식회사
IPC: G11C7/10
CPC classification number: G06F13/161 , G06F13/1657 , G06F13/1694
Abstract: A memory system includes a first memory device, a second memory device, and a memory controller to control the first and second memory devices, wherein the first and second memory devices are discriminated by at least one among a physical distance from the memory controller, connection relationship with the memory controller, error correction capability, and a memory supply voltage, and the first and second memory devices have different latencies.
Abstract translation: 存储器系统包括第一存储器设备，第二存储器设备和用于控制第一和第二存储器设备的存储器控制器，其中第一和第二存储器设备由存储器控制器的物理距离中的至少一个区分，连接 与存储器控制器的关系，纠错能力和存储器电源电压，并且第一和第二存储器件具有不同的延迟。
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公开(公告)号：KR1020140033937A
公开(公告)日：2014-03-19
申请号：KR1020120100513
申请日：2012-09-11
Applicant: 삼성전자주식회사
IPC: G11C7/10
CPC classification number: G06F12/00 , G11C7/1006 , G11C11/4076
Abstract: Disclosed is a semiconductor memory device capable of performing a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on the read data obtained by the read circuit according to the operation assignment information applied through an address line to reduce memory access time when entering the modified read mode. In addition, the semiconductor memory device includes a control circuit to optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.
Abstract translation: 公开了能够执行修改的读取操作或修改的写入操作的半导体存储器件。 半导体存储器件包括存储单元阵列，读取电路和写入电路。 半导体存储器件还包括操作单元，根据通过地址线施加的操作分配信息，对由读取电路获得的读取数据进行操作，以减少进入修改读取模式时的存储器访问时间。 此外，半导体存储器件包括可选地管理正常读取模式和修改读取模式的控制电路，并且允许由操作单元输出的操作结果数据由修改读取模式中的写入电路写入。
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公开(公告)号：KR1020140113117A
公开(公告)日：2014-09-24
申请号：KR1020130028077
申请日：2013-03-15
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
CPC classification number: G11C5/063 , G11C5/025 , G11C11/4093 , G11C11/4097 , G11C2207/105
Abstract: A semiconductor memory device comprises a plurality of input/output pads positioned on a semiconductor substrate and a plurality of memory cell arrays. Each of access times of the memory cell arrays is composed differently proportionally to the length of data passage between the input/output pads and the memory cell arrays. Therefore, a fast access memory area and a low access memory area can be provided within a single memory by having the asymmetric access times based on the physical distance to the input/output pad.
Abstract translation: 半导体存储器件包括位于半导体衬底上的多个输入/输出焊盘和多个存储单元阵列。 存储单元阵列的每个访问时间与输入/输出焊盘和存储单元阵列之间的数据通道的长度不同地组成。 因此，可以通过基于到输入/输出焊盘的物理距离的不对称访问时间，在单个存储器内提供快速存取存储器区域和低访问存储器区域。
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公开(公告)号：KR1020140011147A
公开(公告)日：2014-01-28
申请号：KR1020120077969
申请日：2012-07-17
Applicant: 삼성전자주식회사
IPC: G11C8/00 , G11C11/408 , G11C11/413
CPC classification number: G11C7/1072 , G06F12/0207 , G06F12/0223 , G06F12/0638 , G11C11/005 , G11C11/403 , G11C11/40622 , G11C29/783 , G11C2029/4402
Abstract: In the embodiment according to the concept of the present invention, disclosed is a semiconductor memory cell array. The semiconductor memory cell array includes a first memory cell array area with first group memory cells with preset first operation speeds which are arranged on a chip in a matrix of a row and a column. Also, the semiconductor memory cell array includes a second memory cell array area with second group memory cells with second operation speeds faster than the first operation speeds which are arranged on the chip in the matrix of the row and the column by interposing an input and output sense amplifier. Thereby, the operation performance of a memory chip is improved and low power consumption is obtained.
Abstract translation: 在根据本发明的概念的实施例中，公开了半导体存储单元阵列。 半导体存储单元阵列包括具有第一组存储器单元的第一存储单元阵列区，其具有预定的第一操作速度，其布置在行和列的矩阵中的芯片上。 此外，半导体存储单元阵列包括具有第二组存储单元的第二存储单元阵列区域，第二组存储单元的第二操作速度比通过插入输入和输出的布置在行和列的矩阵中的芯片上的第一操作速度更快 感测放大器。 由此，能够提高存储芯片的动作性能，能够获得低功耗。
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