公开(公告)号：KR1020100077127A

公开(公告)日：2010-07-07

申请号：KR1020097011921

申请日：2008-10-03

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 시바타,가오루 ,  오카바야시,신지 ,  혼주야스히로 ,  이리쿠라마사토 ,  나카니시후미타케

IPC: H01L21/66 ,  H01L21/20

CPC classification number: G01N21/9505 ,  G01N21/894 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor substrate having a uniform semiconductor film. A semiconductor substrate (1) has one or more but not more than 20 pin holes (3) per one semiconductor substrate (1) having a diameter of 2 inches. Thus, effects of warping value reduction of the semiconductor substrate (1) after semiconductor film formation and dimensional variance reduction after exposure are obtained. It is estimated that such effects are brought by having dislocation on the surface of the semiconductor substrate (1) eliminated by existence of the pin hole (3). The film qualities of the semiconductor film are uniformized, performance of a semiconductor device is uniformized, and the semiconductor substrate (1) is prevented from being broken.

Abstract translation: 提供了具有均匀半导体膜的半导体衬底。 半导体衬底（1）具有每个具有2英寸直径的每个半导体衬底（1）中的一个或多个但不超过20个针孔（3）。 因此，获得半导体成膜后的半导体衬底（1）的翘曲值降低和曝光后的尺寸变化减小的效果。 通过存在针孔（3）而消除半导体衬底（1）的表面上的位错，可以估计出这样的效果。 半导体膜的膜质量均匀化，半导体器件的性能均匀化，并且防止半导体衬底（1）破裂。

公开(公告)号：KR1020080022048A

公开(公告)日：2008-03-10

申请号：KR1020070088909

申请日：2007-09-03

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/304 ,  H01L21/20

CPC classification number: C30B33/00 ,  B24B37/04 ,  C09G1/02 ,  C30B29/403 ,  H01L21/02008

Abstract: A method of manufacturing a group III nitride substrate, the group III nitride substrate, the group III nitride substrate with epitaxial layer, a group III nitride device, a method of manufacturing the group III nitride substrate with epitaxial layer, and a method of manufacturing the group III nitride device are provided to further improve the flatness by using an organic acid. Plural stripe type group III nitride substrates(1) are adhered to an abrading holder(53) so that a stripe structure direction is perpendicular to a rotation direction of the abrading holder. The substrate is ground, lapped and/or polished. In the step of polishing the substrates, the substrates are polished by using an abrading surface plate(52) having a pad of which compressibility is 1% - 15%, setting pressure applied from the pad of the abrading surface plate to the substrates to 100g/cm^2 - 1500g/cm^2, and rotating an abrading holder(53) and the abrading surface plate while supplying an abrasive liquid(54) of which pH is 1 - 12.

Abstract translation: 制造III族氮化物衬底，III族氮化物衬底，具有外延层的III族氮化物衬底，III族氮化物器件，具有外延层的III族氮化物衬底的制造方法以及制造方法 提供III族氮化物器件以通过使用有机酸进一步改善平坦度。 多个条状III族氮化物基板（1）被粘附到研磨保持器（53），使得条纹结构方向垂直于研磨保持器的旋转方向。 将基材研磨，研磨和/或抛光。 在研磨基板的步骤中，通过使用具有压缩率为1％〜15％的垫的研磨面板（52），将从研磨面板的焊盘施加的设定压力与基板的基准值设定为100g，研磨基板 / cm 2〜1500g / cm 2，并且在供给pH为1〜12的研磨液（54）的同时旋转研磨保持器（53）和研磨面板。

公开(公告)号：KR1020050033422A

公开(公告)日：2005-04-12

申请号：KR1020040067462

申请日：2004-08-26

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이리쿠라마사토 ,  모치다야스시 ,  나카야마마사히로

IPC: H01L33/22

CPC classification number: H01L21/02013 ,  C30B29/403 ,  H01L21/02395 ,  H01L21/0254 ,  H01L33/0075 ,  H01L33/22 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided to obtain a nitride base semiconductor thin film having the low potential density and the low cost using an epitaxial growth. A surface roughness of a nitride semiconductor substrate is Rms 5nm to 200nm. The surface roughness of a nitride semiconductor substrate is Rms 50nm to 200nm. The nitride semiconductor substrate having a surface roughness of Rms 5nm to 200nm is obtained by lapping using separated or fixed abrasive grains. The nitride semiconductor substrate having a surface roughness of Rms 5nm to 200nm and a potential density of 10.sup.5cm.sup.-2 to 10.sup.9cm.sup.-2, is obtained by lapping using separated or fixed abrasive grains.

Abstract translation: 提供一种氮化物半导体衬底及其制造方法，以使用外延生长获得具有低电位密度和低成本的氮化物基底半导体薄膜。 氮化物半导体衬底的表面粗糙度为5nm至200nm的Rms。 氮化物半导体衬底的表面粗糙度为50nm至200nm的Rms。 具有5nm至200nm的Rms表面粗糙度的氮化物半导体衬底通过使用分离或固定的磨料研磨而获得。 通过使用分离的或固定的磨粒研磨获得表面粗糙度为5nm至200nm，电位密度为10.sup.5cm.sup.2至10.sup.9cm.sup.2的氮化物半导体衬底 。

公开(公告)号：KR1020090066300A

公开(公告)日：2009-06-23

申请号：KR1020097007743

申请日：2007-10-09

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  하치고아키히로 ,  이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/205 ,  H01L21/304 ,  C30B29/38 ,  H01L33/00

CPC classification number: C30B29/403 ,  C30B29/406 ,  C30B33/00 ,  H01L21/02024 ,  H01L33/16 ,  H01L33/32

Abstract: A Group III element nitride substrate on which an epitaxial layer of good quality can be grown; and a process for producing the substrate. The Group III element nitride substrate may be a GaN substrate (1) which satisfies any of the following requirements. It has a surface (3) in which the number of atoms constituting any acid substance(s) is 2X1014 or smaller per cm2 and the number of silicon atoms is 3X1013 or smaller per cm2. It has a surface (3) in which the number of silicon atoms is 3X1013 or smaller per cm2 and which has a haze level of 5 ppm or less. It has a surface (3) in which the number of atoms constituting any acid substance(s) is 2X1014 or smaller per cm2 and which has a haze level of 5 ppm or less.

Abstract translation: 可以生长质量好的外延层的III族元素氮化物衬底; 以及基板的制造方法。 III族元素氮化物衬底可以是满足以下任何一个要求的GaN衬底（1）。 其表面（3）其中构成任何酸性物质的原子数为每平方厘米2×10 14或更小，硅原子数为3×10 13或更小每平方厘米。 其表面（3）的硅原子数为3×10 13以下/ cm 2，雾度为5ppm以下。 其表面（3）其中构成任何酸性物质的原子数目为每平方厘米2×1014或更小，并且雾度水平为5ppm以下。

公开(公告)号：KR1020090052291A

公开(公告)日：2009-05-25

申请号：KR1020080115323

申请日：2008-11-19

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/302 ,  H01L21/304

CPC classification number: H01L29/045 ,  B82Y20/00 ,  C30B29/406 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66712 ,  H01L29/7787 ,  H01L29/7802 ,  H01L29/872 ,  H01L33/16 ,  H01L33/20 ,  H01L33/32 ,  H01S5/22 ,  H01S5/34333

Abstract: A GaN substrate manufacturing method characterized in including a step of processing the surface of a substrate composed of a GaN single crystal into a concavely spherical form, based on differences in orientation of the crystallographic axis across the substrate surface. Processing the GaN substrate surface into a concavely spherical form reduces, in the post-process GaN substrate surface, differences in orientation of the crystallographic axis with respect to a normal. Furthermore, employing to manufacture semiconductor devices a GaN substrate in which differences in orientation of the crystallographic axis have been reduced makes it possible to uniformize in device characteristics a plurality of semiconductor devices fabricated from a single GaN substrate, which contributes to improving yields in manufacturing the semiconductor devices.

公开(公告)号：KR101308328B1

公开(公告)日：2013-09-17

申请号：KR1020097007743

申请日：2007-10-09

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  하치고아키히로 ,  이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/205 ,  H01L21/304 ,  C30B29/38 ,  H01L33/00

CPC classification number: C30B29/403 ,  C30B29/406 ,  C30B33/00 ,  H01L21/02024 ,  H01L33/16 ,  H01L33/32

Abstract: 본 발명에 따르면 양호한 품질의 에피택셜 성장층을 형성하는 것이 가능한 III족 질화물 기판 및 그 제조 방법을 얻을 수 있다. III족 질화물 기판으로서의 GaN 기판(1)은 이하 중 어느 하나의 것이다. 표면(3)의 1 ㎠당 산성 물질의 원자의 갯수가 2×10
14 이하이며, 상기 표면(3)의 1 ㎠당 실리콘 원자의 갯수가 3×10
13 이하이다. 표면(3)의 1 ㎠당 실리콘 원자의 갯수가 3×10
13 이하이며, 상기 표면(3)의 헤이즈 레벨(haze level)은 5 ppm 이하이다. 표면(3)의 1 ㎠당 산성 물질의 원자의 갯수가 2×10
14 이하이며, 상기 표면(3)의 헤이즈 레벨은 5 ppm 이하이다.

公开(公告)号：KR1020090115667A

公开(公告)日：2009-11-05

申请号：KR1020090036128

申请日：2009-04-24

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  마츠모토나오키 ,  이리쿠라마사토

IPC: H01L21/302

CPC classification number: H01L21/02013 ,  C30B29/403 ,  C30B33/00 ,  H01L21/02024 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A group III nitride crystal, and a surface processing method thereof, a group III nitride laminate, a manufacturing method thereof, a group III nitride semiconductor device and the manufacturing method thereof are provided to reduce impurity of a crystal surface by removing a hard grain in the crystal after lapping. CONSTITUTION: A surface of group III nitride crystal is lapped using the hard grain with the higher mohshardness than 7. The lapped surface of the group III nitride crystal is polished using the polishing solution without the grain. The pH of the polishing solution without the grain is between 1 and 6 or 8.5 and A laminate structure is comprised of a Ni layer with the 4 nm and an Au layer with 4 nm as a second electrode(662) on a p type GaN(632). The second electrode is bonded in a conductor(682) with a soldering layer(670). A first electrode(661) and the conductor(681) are bonded with a wire(690).

Abstract translation: 目的：提供III族氮化物晶体及其表面处理方法，III族氮化物层压体，其制造方法，III族氮化物半导体器件及其制造方法，以通过去除硬的来降低晶体表面的杂质 研磨后的晶体颗粒。 构成：使用硬度高于7的硬质晶粒研磨III族氮化物晶体的表面。使用不含晶粒的抛光溶液抛光III族氮化物晶体的重叠表面。 没有颗粒的抛光液的pH值在1到6或8.5之间，层压结构由4nm的Ni层和4nm的Au层组成，作为ap型GaN（632）上的第二电极（662） ）。 第二电极通过焊接层（670）接合在导体（682）中。 第一电极（661）和导体（681）用导线（690）结合。

公开(公告)号：KR1020080006446A

公开(公告)日：2008-01-16

申请号：KR1020070043610

申请日：2007-05-04

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/304 ,  H01L21/20

CPC classification number: H01L21/02013 ,  B24B37/042 ,  H01L21/02027 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/0657 ,  H01L2221/6834 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A group 3 nitride substrate wafer and a manufacturing method thereof are provided to decrease surface roughness of the substrate wafer by arranging a surface slant of a substrate to be smaller than 200 mum in a horizontal direction and 100 mum in a vertical direction. Plural group 3 nitride substrate wafers having an OF(Orientation Flat) with a length between 2 and 30 mm and a diameter greater than 40 mm are attached to a polishing plate by using a wax with a thickness smaller than 10 mum. The OF is polished to face a front, rear, or inner portion with respect to a rotation direction. A surface slant of the substrate is smaller than 200 mum in a horizontal direction and smaller than 100 mum in a vertical direction.

Abstract translation: 提供第3族氮化物衬底晶片及其制造方法，通过将衬底的表面倾斜度在水平方向上设置为小于200μm，在垂直方向上设置为100μm，来降低衬底晶片的表面粗糙度。 通过使用厚度小于10um的蜡将具有长度为2至30mm且直径大于40mm的OF（取向平面）的多组3氮化物衬底晶片附接到抛光板。 OF被抛光以相对于旋转方向面对前，后或内部。 基板的表面倾斜在水平方向上小于200μm，在垂直方向上小于100μm。

公开(公告)号：KR1020070115666A

公开(公告)日：2007-12-06

申请号：KR1020070051858

申请日：2007-05-29

Applicant: 스미토모덴키고교가부시키가이샤

Inventor： 이시바시게이지 ,  니시우라다카유키 ,  이리쿠라마사토 ,  나카하타세이지

IPC: H01L21/304 ,  H01L33/32

CPC classification number: H01L21/02024 ,  C09G1/02 ,  C30B29/406 ,  C30B33/00 ,  H01L21/02052 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/1305 ,  Y10S438/959 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface treatment method of a nitride crystal, a nitride crystal substrate, the nitride crystal substrate with an epitaxial layer and a semiconductor device, and a method for manufacturing the nitride crystal substrate with the epitaxial layer and the semiconductor device are provided to form a flat surface having a good quality on the nitride crystal. A nitride crystal(1) is polished by performing CMP using abrasive grains(16) of oxide. The abrasive grains have a standard free energy of formation of at least -850 kJ/mol as a converted value per 1 mole of oxygen molecules. And the abrasive grains have a Mohs hardness of at least 4.

Abstract translation: 氮化物晶体的表面处理方法，氮化物晶体衬底，具有外延层的氮化物晶体衬底和半导体器件以及用于制造具有外延层和半导体器件的氮化物晶体衬底的方法被提供以形成平坦 表面在氮化物晶体上具有良好的质量。 通过使用氧化物的磨粒（16）进行CMP来研磨氮化物晶体（1）。 作为每1摩尔氧分子的转化值，磨粒具有形成至少-850kJ / mol的标准自由能。 磨粒的莫氏硬度至少为4。