公开(公告)号：KR1020080071822A

公开(公告)日：2008-08-05

申请号：KR1020070010165

申请日：2007-01-31

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  송재영

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L29/4236 ,  H01L29/66575 ,  H01L29/785

Abstract: A FIREFET(Fin and Recess channel MOSFET) and a manufacturing method thereof are provided to improve a current driving performance of the FIREFET by reducing source and drain resistances. An active region is surrounded by a field oxide film on a semiconductor substrate. Source/drain(14,16) are formed on the active region with a fin-type channel between them. A recess hole is formed under the source/drain and the fin channel. A recess channel is formed under the fin channel at one side of the recess hole. Gate oxide films(80) are formed on a surface of the recess hole including the recess channel, side surfaces of the source/drain, and the fin channel. A gate(90a) surrounds the recess channel and the fin channel on the gate oxide film and is formed between the recess hole and the source/drain.

Abstract translation: 提供了一种FIREFET（Fin和Recess通道MOSFET）及其制造方法，以通过减少源极和漏极电阻来提高FIREFET的电流驱动性能。 有源区被半导体衬底上的场氧化膜包围。 源极/漏极（14,16）形成在有源区域上，在它们之间具有鳍状沟道。 在源极/漏极和鳍片通道下方形成凹陷孔。 在凹槽的一侧的翅片通道下方形成凹槽。 栅极氧化膜（80）形成在包括凹槽的凹槽的表面上，源/漏和鳍通道的侧表面。 栅极（90a）围绕凹槽通道和栅氧化膜上的散热片通道，并形成在凹槽和源极/漏极之间。

公开(公告)号：KR100804738B1

公开(公告)日：2008-02-19

申请号：KR1020070004973

申请日：2007-01-16

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 고형수 ,  박병국 ,  홍승범 ,  박철민 ,  최우영 ,  김종필 ,  송재영 ,  김상완

IPC: H01L21/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  G01R1/067

Abstract: A semiconductor probe using an impact-ionization semiconductor device is provided to remarkably improve the limit of sensitivity of a resistive probe and easily adjust the quantity of charges capable of being detected by a probe by developing a new probe structure for easily adjusting the band energy of a source. One tilted surface of a probe is formed by an anisotropic etch process using a first etch mask pattern formed on a silicon substrate. After impurities are doped into the exposed substrate to form a first semiconductor electrode region(16), the first etch mask pattern is removed. A second etch mask pattern opposite to the direction of the first etch mask pattern is formed on the silicon substrate. Space layers are formed on the sidewalls of the second etch mask pattern. After the exposed silicon substrate is anisotropically etched to form an opposite tilted surface of the probe, the second etch mask pattern is removed. Impurities are doped into the exposed substrate to form a second semiconductor electrode region(18), and the second etch mask pattern is removed. A silicon oxide layer pattern is formed on the resultant structure by a known method. Space layers are formed on both sidewalls of the silicon oxide layer pattern. By using the space layer, a predetermined depth of the silicon substrate is etched by a photolithography process, and the space layer is removed. The first semiconductor electrode region can be a source terminal, and the second semiconductor electrode region can be a drain terminal.

Abstract translation: 提供使用冲击电离半导体器件的半导体探针，以显着提高电阻式探头的灵敏度极限，并且通过开发新的探针结构容易地调节能够由探针检测的电荷量，从而容易地调节带电能 来源。 通过使用形成在硅衬底上的第一蚀刻掩模图案的各向异性蚀刻工艺形成探针的一个倾斜表面。 在将杂质掺杂到暴露的衬底中以形成第一半导体电极区域（16）之后，去除第一蚀刻掩模图案。 在硅衬底上形成与第一蚀刻掩模图案的方向相反的第二蚀刻掩模图案。 空间层形成在第二蚀刻掩模图案的侧壁上。 在暴露的硅衬底被各向异性蚀刻以形成探针的相对的倾斜表面之后，去除第二蚀刻掩模图案。 将杂质掺杂到暴露的衬底中以形成第二半导体电极区域（18），并且去除第二蚀刻掩模图案。 通过已知的方法在所得结构上形成氧化硅层图案。 空间层形成在氧化硅层图案的两个侧壁上。 通过使用空间层，通过光刻工艺蚀刻硅衬底的预定深度，并且去除空间层。 第一半导体电极区域可以是源极端子，第二半导体电极区域可以是漏极端子。

公开(公告)号：KR100842923B1

公开(公告)日：2008-07-03

申请号：KR1020070022550

申请日：2007-03-07

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 고형수 ,  박병국 ,  홍승범 ,  박철민 ,  최우영 ,  김종필 ,  송재영 ,  김상완

IPC: G11B9/14 ,  G11B9/02

CPC classification number: H01L29/7834 ,  B82Y10/00 ,  G11B9/1409 ,  H01L21/28123 ,  H01L29/66636

Abstract: A method of manufacturing an enhancement semiconductor probe and an information storage device using the same are provided to reduce a process variable in device performance and to increase reliability of mass production by anisotropic-wet-etching a silicon substrate using side-walls. A method of manufacturing an enhancement semiconductor probe comprises the steps of: forming a first etching mask pattern(110a) on a silicon substrate(100c) to form a tip part of the probe in a first direction and forming side-wall areas at two sides of the first etching mask pattern; anisotropic-etching the silicon substrate to form two inclined surfaces of the probe; forming source and drain areas(160,170,180,190) on the silicon substrate by injecting dopants, using the side-wall area as masks, and removing the side-wall areas; removing the first etching mask pattern; forming a second etching mask pattern to form a tip part of the probe in a second direction; forming space layers at two sides of the second etching mask pattern; and etching the silicon substrate by photographing and etching processes and removing the space layers.

Abstract translation: 提供一种制造增强半导体探针的方法和使用其的信息存储装置，以减少器件性能中的工艺变量，并且通过使用侧壁对硅衬底进行各向异性湿蚀刻来提高批量生产的可靠性。 一种制造增强型半导体探针的方法包括以下步骤：在硅衬底（100c）上形成第一蚀刻掩模图案（110a），以在第一方向上形成探针的尖端部分，并在两侧形成侧壁区域 的第一蚀刻掩模图案; 各向异性蚀刻硅衬底以形成探针的两个倾斜表面; 通过注入掺杂剂在硅衬底上形成源极和漏极区域（160,170,180,190），使用侧壁区域作为掩模，并去除侧壁区域; 去除第一蚀刻掩模图案; 形成第二蚀刻掩模图案以在第二方向上形成探针的末端部分; 在第二蚀刻掩模图案的两侧形成空间层; 并通过拍摄和蚀刻工艺蚀刻硅衬底并去除空间层。

公开(公告)号：KR100855870B1

公开(公告)日：2008-09-03

申请号：KR1020070010165

申请日：2007-01-31

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  송재영

IPC: H01L21/336

Abstract: 본 발명은 핀과 리세스 혼합 채널 영역을 가진 전계효과트랜지스터 및 그 제조방법에 관한 것으로, 벌크 기판 위에 넓은 소스/드레인 면적과 자기 정렬형으로 구현된 핀 및 리세스 혼합 채널 MOSFET 구조를 가짐으로써, 전류 구동 능력을 근본적으로 향상시킨 새로운 FIREFET 소자 구조와 비교적 간단한 공정 방법으로 소스/드레인과 게이트 사이를 자기 정렬형으로 제조할 수 있는 상기 FIREFET 소자의 제조방법이 개시된다.
핀, 리세스, FinFET, MOSFET