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公开(公告)号：KR100463028B1
公开(公告)日：2004-12-23
申请号：KR1020020016134
申请日：2002-03-25
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/74
Abstract: PURPOSE: A MOS(Metal-Oxide-Semiconductor) controlled thyristor is provided to be capable of increasing the maximum controllable current of the MOS controlled thyristor and restraining the snap-back phenomenon of the MOS controlled thyristor by using a trench gate structure. CONSTITUTION: A MOS controlled thyristor is provided with a trench gate(203) for simultaneously forming a finger gate and a main gate by etching a plurality of trenches to the vertical direction of the trench gate before forming the trench gate and a P-type base(201) self-aligned by using the trench gate as a mask. At this time, the channel width of the main gate is increased through the trench gate. Preferably, a plurality of trenches are formed at the trench gate.
Abstract translation: 目的：提供MOS（金属氧化物半导体）控制晶闸管，以便能够通过使用沟槽栅极结构来增加MOS控制晶闸管的最大可控电流并抑制MOS控制晶闸管的回跳现象。 本发明的MOS控制晶闸管具有沟槽栅极（203），用于在形成沟槽栅极和P型基极之前，通过在沟槽栅极的垂直方向上蚀刻多个沟槽来同时形成指栅极和主栅极 （201）通过使用沟槽栅作为掩模来自对准。 此时，主栅极的沟道宽度通过沟槽栅极增加。 优选地，在沟槽栅极处形成多个沟槽。
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公开(公告)号：KR100463029B1
公开(公告)日：2004-12-23
申请号：KR1020020016135
申请日：2002-03-25
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/74
Abstract: PURPOSE: A horizontal type thyristor is provided to be capable of improving forward current saturation characteristics and obtaining fast switching characteristics for reducing power consumption at turn-off state. CONSTITUTION: A horizontal type thyristor is provided with a substrate(430), an anode and a cathode formed at the upper portion of the substrate, the first N+ type region(402) formed at the lower portion of the anode, a P+ type region(404a) formed at the lower portion of an FOC(Floating Ohmic Contact), and the second N+ type region(404b) formed at the lower portion of the anode for being electrically connected with the P+ region formed at the lower portion of the FOC. At this time, electrons are flowed from the second N+ type region by flowing holes having the same quantity of the electrons into the P+ type region, according to the principle of charge neutrality.
Abstract translation: 目的：提供一种水平型晶闸管，能够改善正向电流饱和特性并获得快速开关特性，以降低关断状态下的功耗。 本发明公开了一种水平型晶闸管，其包括衬底（430），形成在衬底上部的阳极和阴极，形成在阳极下部的第一N +型区域（402），形成在衬底上的P +型区域 在FOC（浮动欧姆接触）的下部形成的第一N +型区域（404a）和形成在阳极下部的第二N +型区域（404b），用于与在FOC的下部形成的P +区域电连接 。 此时，根据电荷中性原理，通过使具有相同量的电子的空穴流入P +型区域，电子从第二N +型区域流动。
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公开(公告)号：KR1020020071574A
公开(公告)日：2002-09-13
申请号：KR1020010011687
申请日：2001-03-07
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: An SOI(Silicon On Insulator) LDMOSFET(Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) is provided to improve trade-off characteristics of a breakdown voltage and an on-resistance by using a vacuum layer as a buried layer. CONSTITUTION: An SOI LDMOSFET comprises a source electrode(41), a drain electrode(43), a gate electrode(42), a P-body(32) and an N-drift region(30). At this time, a buried layer having a vacuum layer in a defined portion is formed under the P-body(32) and the N-drift region(30). At this time, the buried layer comprises a buried vacuum layer(61) formed with the vacuum layer and a buried oxidation layer(62) formed with an oxidation layer.
Abstract translation: 目的：提供SOI（绝缘体上硅）LDMOSFET（横向双扩散金属氧化物半导体场效应晶体管），通过使用真空层作为掩埋层来提高击穿电压和导通电阻的折衷特性。 构成：SOI LDMOSFET包括源电极（41），漏电极（43），栅电极（42），P体（32）和N漂移区（30）。 此时，在P体（32）和N漂移区（30）的下方形成具有限定部分的真空层的掩埋层。 此时，埋层包括由真空层形成的掩埋真空层（61）和形成有氧化层的掩埋氧化层（62）。
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公开(公告)号：KR100485131B1
公开(公告)日：2005-04-25
申请号：KR1020020063873
申请日：2002-10-18
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/70
Abstract: 본 발명은 반도체 소자의 접합 마감(junction termination) 기술에 관한 것으로, 특히 반도체 소자의 항복전압 특성 개선을 위한 실리콘 산화막 트렌치와 전계 제한 확산링(Floating Field Limiting Ring: 이하 FLR이라 칭함)을 이용한 반도체 소자의 접합 마감 구조에 관한 것이다.
본 발명의 접합 마감 구조는 제1 도전형의 반도체층과; 상기 제1 도전형의 반도체층에 형성된 제2 도전형의 주접합영역과; 상기 주접합영역과 간격을 두고, 각각 서로 이격 되어 형성된 적어도 하나 이상의 제2 도전형의 접합 마감 영역(FLR: floating feld limiting ring) 및 소자의 항복전압 특성을 개선하기 위해, 상기 주접합영역과 상기 접합 마감 영역 사이 또는 상기 적어도 하나 이상의 접합 마감 영역들 사이에 형성된 트렌치 구조의 절연층을 포함하는 것을 특징으로 한다.-
公开(公告)号：KR1020040035131A
公开(公告)日：2004-04-29
申请号：KR1020020063873
申请日：2002-10-18
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/70
Abstract: PURPOSE: A junction termination structure of a semiconductor device is provided to boost a breakdown voltage without increasing a size of the semiconductor device by using a silicon oxide trench and a floating field limiting ring to form the junction termination structure. CONSTITUTION: A junction termination structure of a semiconductor device includes a first conductive type semiconductor layer, a second conductive type active region, one or more second conductive type junction terminal regions, and an insulating layer. The second conductive type active region is formed on the first conductive type semiconductor layer. The second conductive type junction terminal regions are formed at a predetermined position apart from the second conductive type junction terminal regions. The insulating layer is formed between the second conductive type junction terminal regions within the first conductive type semiconductor layer.
Abstract translation: 目的：提供半导体器件的接线端接结构，以通过使用氧化硅沟槽和浮动场限制环来形成接合端接结构来提高击穿电压而不增加半导体器件的尺寸。 构成：半导体器件的接合端接结构包括第一导电类型半导体层，第二导电型有源区，一个或多个第二导电型结端子区和绝缘层。 第二导电型有源区形成在第一导电型半导体层上。 第二导电型结端子区域形成在与第二导电型结端子区域隔开的预定位置处。 绝缘层形成在第一导电类型半导体层内的第二导电型结端子区域之间。
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Patent Agency Ranking
公开(公告)号：KR1020030077187A
公开(公告)日：2003-10-01
申请号：KR1020020016135
申请日：2002-03-25
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/74
Abstract: PURPOSE: A horizontal type thyristor is provided to be capable of improving forward current saturation characteristics and obtaining fast switching characteristics for reducing power consumption at turn-off state. CONSTITUTION: A horizontal type thyristor is provided with a substrate(430), an anode and a cathode formed at the upper portion of the substrate, the first N+ type region(402) formed at the lower portion of the anode, a P+ type region(404a) formed at the lower portion of an FOC(Floating Ohmic Contact), and the second N+ type region(404b) formed at the lower portion of the anode for being electrically connected with the P+ region formed at the lower portion of the FOC. At this time, electrons are flowed from the second N+ type region by flowing holes having the same quantity of the electrons into the P+ type region, according to the principle of charge neutrality.
Abstract translation: 目的：提供一种水平型晶闸管，能够提高正向电流饱和特性，并获得快速的开关特性，以减少关断状态下的功耗。 构造：水平型晶闸管设置有形成在基板的上部的基板（430），阳极和阴极，形成在阳极的下部的第一N +型区域（402），P +型区域 形成在FOC（浮动欧姆接触件）的下部的第二N +型区域（404a）和形成在阳极下部的第二N +型区域（404b），用于与形成在FOC的下部的P +区域电连接 。 此时，根据电荷中性原理，电子通过将具有相同量的电子的空穴流入P +型区域而从第二N +型区域流出。
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公开(公告)号：KR100522519B1
公开(公告)日：2005-10-18
申请号：KR1020020031918
申请日：2002-06-07
Applicant: 재단법인서울대학교산학협력재단 , 매그나칩 반도체 유한회사
IPC: H01L29/74
Abstract: 본 발명은 사이리스터(Thyristor)로 동작하는 고전압 소자 구조에 게이트 커플링을 사용하며, 정전기 보호 사이리스터에 있어서, 고전압 소자의 특성에 따른 입/출력 신호의 상승/하강 시간과 ESD 펄스의 상승/하강 시간의 차이에 따라 상기 게이트 커플링 동작이 이루어지도록 필드 산화막 또는 두꺼운 산화막을 게이트 산화막으로 사용한다.
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公开(公告)号：KR1020050051274A
公开(公告)日：2005-06-01
申请号：KR1020030085035
申请日：2003-11-27
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/73
Abstract: 본 발명은 전극이 칩 전면에 위치하는 수평형 절연게이트 바이폴라 트랜지스터에 관한 것이다.
본 발명의 수평형 절연게이트 바이폴라 트랜지스터는 소스 영역 내에 트렌치를 형성하여 소스 영역이 부분적으로 중단되도록 함으로써 소스 영역을 감싸고 있는 베이스 영역의 저항을 부분적으로 낮추어 주어 기생 사이리스트의 래치-업을 낮추도록 한다. 또한, 게이트 전극을 트렌치 내에 연장되도록 형성함으로써 유효 채널 폭을 증가시켜 순방향 전압 강하의 증가 없이 기생 사이리스터 래치-업을 억제 할 수 있도록 한다.-
公开(公告)号：KR1020030094673A
公开(公告)日：2003-12-18
申请号：KR1020020031918
申请日：2002-06-07
Applicant: 재단법인서울대학교산학협력재단 , 매그나칩 반도체 유한회사
IPC: H01L29/74
Abstract: PURPOSE: An electrostatic discharge(ESD) protection thyristor is provided to reduce a trigger voltage of a thyristor and improve an ESD characteristic by forming a gate-coupled thyristor(GCT) using a gate coupling concept in a device structure functioning as the thyristor. CONSTITUTION: The ESD protection thyristor uses a field oxide layer or a thick oxide layer as a gate oxide layer, including a gate coupling thyristor structure to prevent static electricity of a high voltage device. The gate coupling operation is performed according to a difference of time interval between the rising/falling time of an input/output signal and the rising/falling time of an ESD pulse.
Abstract translation: 目的：提供一种静电放电（ESD）保护晶闸管，以减少晶闸管的触发电压，并通过在用作晶闸管的器件结构中使用栅极耦合概念形成栅极耦合晶闸管（GCT）来提高ESD特性。 构成：ESD保护晶闸管使用场氧化物层或厚氧化物层作为栅极氧化层，包括栅极耦合晶闸管结构，以防止高压器件的静电。 根据输入/输出信号的上升/下降时间与ESD脉冲的上升/下降时间之间的时间间隔的差异执行栅极耦合操作。
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公开(公告)号：KR100403519B1
公开(公告)日：2003-10-30
申请号：KR1020010011687
申请日：2001-03-07
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: An SOI(Silicon On Insulator) LDMOSFET(Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) is provided to improve trade-off characteristics of a breakdown voltage and an on-resistance by using a vacuum layer as a buried layer. CONSTITUTION: An SOI LDMOSFET comprises a source electrode(41), a drain electrode(43), a gate electrode(42), a P-body(32) and an N-drift region(30). At this time, a buried layer having a vacuum layer in a defined portion is formed under the P-body(32) and the N-drift region(30). At this time, the buried layer comprises a buried vacuum layer(61) formed with the vacuum layer and a buried oxidation layer(62) formed with an oxidation layer.
Abstract translation: 目的：提供SOI（绝缘体上硅）LDMOSFET（横向双扩散金属氧化物半导体场效应晶体管），以通过使用真空层作为掩埋层来提高击穿电压和导通电阻的折衷特性。 构成：SOI LDMOSFET包括源电极（41），漏电极（43），栅电极（42），P体（32）和N漂移区（30）。 此时，在P体（32）和N漂移区（30）下方形成在限定部分中具有真空层的掩埋层。 此时，埋层包括由真空层形成的埋入真空层（61）和由氧化层形成的埋入氧化层（62）。
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