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    一种形成半导体器件的双重结构的方法及其半导体器件

    公开(公告)号:KR1020140083696A

    公开(公告)日:2014-07-04

    申请号:KR1020120153753

    申请日:2012-12-26

    Abstract: Provided is a method for forming a dual damascene structure of a semiconductor element which is as follows: (a) first and second insulation layers are sequentially formed on a substrate; (b) a resist mask with a pattern for forming a via-hole is formed on the second insulation layer; (c) a via-hole is formed to a bottom of the first insulation layer; (d) a hard mask layer is formed on the via-hole and the second insulation layer by using a spin-on-coating method; (e) a resist mask with a pattern for forming a trench hole is formed on the hard mask layer; (f) a first trench hole is formed to a bottom of the second insulation layer through the resist mask; (g) each of portions of a hard mask layer, which are formed on the via-hole and the second insulation layer, are removed; (h) a portion of the second insulation layer between a top corner of the via-hole (via top corner) and a bottom corner of the first trench hole (trench bottom corner) is removed to form a second trench hole; (i) a remaining hard mask layer, which is formed on the via-hole and the second insulation layer, is removed; and (j) the via-hole and the second trench hole are buried with a conductive material, such that an upper interconnection is formed.

    Abstract translation: 提供一种用于形成半导体元件的双镶嵌结构的方法,其如下:(a)第一和第二绝缘层依次形成在基板上; (b)在第二绝缘层上形成具有用于形成通孔的图案的抗蚀剂掩模; (c)在第一绝缘层的底部形成通孔; (d)使用旋涂法在通孔和第二绝缘层上形成硬掩模层; (e)在硬掩模层上形成具有用于形成沟槽的图案的抗蚀剂掩模; (f)通过抗蚀剂掩模,在第二绝缘层的底部形成第一沟槽; (g)去除形成在通孔和第二绝缘层上的硬掩模层的各部分; (h)去除所述通孔的顶角(经由顶角)和所述第一沟槽的底角(沟槽底角)之间的所述第二绝缘层的一部分,以形成第二沟槽; (i)除去形成在通孔和第二绝缘层上的剩余硬掩模层; 和(j)通孔和第二沟槽用导电材料掩埋,从而形成上互连。

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