公开(公告)号：WO2012018799A3

公开(公告)日：2012-05-24

申请号：PCT/US2011046246

申请日：2011-08-02

Applicant: ALTERA CORP ,  LEE ANDY L ,  WATT JEFFREY T

Inventor： LEE ANDY L ,  WATT JEFFREY T

IPC: H03K19/173 ,  G06F9/06

CPC classification number: H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract translation: 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：DE602007012165D1

公开(公告)日：2011-03-10

申请号：DE602007012165

申请日：2007-04-20

Applicant: ALTERA CORP

Inventor： LEWIS DAVID ,  NGO NINH D ,  LEE ANDY L ,  HUANG JOSEPH

IPC: G11C29/52 ,  G06F11/10 ,  H03K19/177

公开(公告)号：GB2321989A

公开(公告)日：1998-08-12

申请号：GB9801182

申请日：1998-01-20

Applicant: ALTERA CORP

Inventor： MCCLINTOCK CAMERON R ,  LEE ANDY L ,  CLIFF RICHARD G

IPC: G06F11/20 ,  G11C29/00 ,  H03K19/177

Abstract: Redundant circuitry for a logic circuit such as a programmable logic device allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic area 22a. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

公开(公告)号：DE69933525D1

公开(公告)日：2006-11-23

申请号：DE69933525

申请日：1999-11-15

Applicant: ALTERA CORP

Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

公开(公告)号：US6411124B2

公开(公告)日：2002-06-25

申请号：US76160201

申请日：2001-01-16

Applicant: ALTERA CORP

Inventor： LEE ANDY L ,  JOHNSON BRIAN ,  CLIFF RICHARD G

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/1774

Abstract: A logic module for a programmable logic device includes shift register circuitry in addition to the conventional programmable memory cells and look-up table decoder or selection control circuitry. In one embodiment the selection control circuitry can access either the memory cells or the various stages of the shift register. The shift register stages, and preferably the master and slave latches of each shift register stage, are accessed in a Gray code order. All of the stages of the shift register are preferably clearable in parallel. The shift registers of two logic modules are preferably cascadable to facilitate providing longer shift registers. Clock circuitry may be provided to facilitate providing two clock signals that are the logical inverse of one another with a common enable signal.

Abstract translation: 用于可编程逻辑器件的逻辑模块除了传统的可编程存储器单元和查找表解码器或选择控制电路之外还包括移位寄存器电路。 在一个实施例中，选择控制电路可以访问移位寄存器的存储单元或各个级。 移位寄存器级，优选地，每个移位寄存器级的主锁存器和从锁存器以格雷码顺序被访问。 移位寄存器的所有阶段优选并行地可清除。 两个逻辑模块的移位寄存器优选地可级联以便于提供更长的移位寄存器。 可以提供时钟电路以便于提供具有公共使能信号的彼此逻辑反相的两个时钟信号。

公开(公告)号：DE69933525T2

公开(公告)日：2007-04-05

申请号：DE69933525

申请日：1999-11-15

Applicant: ALTERA CORP

Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

公开(公告)号：GB2321989B

公开(公告)日：2000-10-18

申请号：GB9801182

申请日：1998-01-20

Applicant: ALTERA CORP

Inventor： MCCLINTOCK CAMERON R ,  LEE ANDY L ,  CLIFF RICHARD G

IPC: G06F11/20 ,  G11C29/00 ,  H03K19/177

公开(公告)号：JP2005229650A

公开(公告)日：2005-08-25

申请号：JP2005121750

申请日：2005-04-19

Applicant: Altera Corp ,  アルテラ・コーポレーション

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture capable of arranging an IP functional block so as to optimize the routing architecture of a base signal. SOLUTION: A programmable logic device (PLD) is provided with a plurality of logical elements (LE) constituted into an array and the routing architecture of the base signal provided with a plurality of signal-routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part and the routing architecture of the base signal is at least partially interrupted at the hole. The PLD is further provided with an interface circuit inside the peripheral part of the hole, and the interface circuit can be constituted so as to connect a circuit inside the hole to the architecture of routing the signal. The PLD is provided with the IP functional block inside the hole further and is electrically connected to the interface circuit. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够布置IP功能块以便优化基本信号的路由架构的PLD架构。 解决方案：可编程逻辑器件（PLD）被提供有构成阵列的多个逻辑元件（LE），并且基本信号的路由架构具有多个信号路由线，用于在LE之间路由信号 。 在LE的阵列内部形成一个孔，孔由外围部分和中心部分组成，基部信号的路由结构在孔处至少部分中断。 PLD还在孔的周边部分内设置有接口电路，并且接口电路可以构成为将孔内的电路连接到路由信号的架构。 PLD还在孔内部设置有IP功能块，并且电连接到接口电路。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2007293856A

公开(公告)日：2007-11-08

申请号：JP2007112429

申请日：2007-04-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LEWIS DAVID ,  NGO NINH D ,  LEE ANDY L ,  HUANG JOSEPH

IPC: G06F12/16 ,  G06F11/08 ,  G06F11/30 ,  H03K19/177

CPC classification number: G11C29/52 ,  G06F11/1064 ,  H03K19/17764

Abstract: PROBLEM TO BE SOLVED: To provide a method for detecting an error in a configuration memory of a programmable device. SOLUTION: The method for detecting errors in the configuration memory of the programmable device includes: reading configuration memory data from the configuration memory; determining whether an error occurs in the configuration memory data; reading sensitivity data corresponding to the configuration data being the error in response to determination that the error occurs; analyzing the sensitivity data in order to determine whether the error can be ignored; starting a remedial activity when the error can not be ignored; and ignoring the error by not starting the repair activity when the error can be ignored. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于检测可编程设备的配置存储器中的错误的方法。 解决方案：用于检测可编程设备的配置存储器中的错误的方法包括：从配置存储器读取配置存储器数据; 确定配置存储器数据中是否发生错误; 响应于发生错误的确定，对应于作为错误的配置数据的读取敏感度数据; 分析灵敏度数据，以确定误差是否可以忽略; 当错误不能忽略时开始补救活动; 并且当错误可以忽略时，通过不启动修复活动来忽略该错误。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007081426A

公开(公告)日：2007-03-29

申请号：JP2006320925

申请日：2006-11-28

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture which allows an IP functional block to be arranged to optimize the routing architecture of base signals. SOLUTION: This programmable logical device (PLD) is provided with a plurality of logical elements(LEs) constituted into an array and the routing architecture of the base signals provided with a plurality of signal routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part, the routing architecture of the base signals is at least partially interrupted at the hole, and the PLD is further provided with an interface circuit inside the peripheral part of the hole. The interface circuit can be constituted so that a circuit inside the hole is coupled to the architecture of routing the signals, and the PLD is further provided with the IP functional block inside the hole and is electrically coupled to the interface circuit. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种PLD架构，其允许IP功能块被布置成优化基本信号的路由架构。 解决方案：该可编程逻辑器件（PLD）被提供有构成阵列的多个逻辑元件（LE），并且基准信号的路由架构设置有用于在LE之间路由信号的多个信号路由线。 在LE的阵列内部形成一个孔，孔由周边部分和中心部分组成，基本信号的路由结构在孔处至少部分中断，并且PLD还具有接口电路 在孔的周边部分内。 接口电路可以构成为使得孔内的电路耦合到路由信号的架构，并且PLD还在孔内设置有IP功能块，并且电耦合到接口电路。 版权所有（C）2007，JPO＆INPIT