Abstract:
Described herein is a method of determining assist features for a mask pattern. The method includes obtaining (i) a target pattern comprising a plurality of target features, wherein each of the plurality of target features comprises a plurality of target edges, and (ii) a trained sequence-to-sequence machine leaning (ML) model (e.g., long short term memory, Gated Recurrent Units, etc.) configured to determine sub-resolution assist features (SRAFs) for the target pattern. For a target edge of the plurality of target edges, geometric information (e.g., length, width, distances between features, etc.) of a subset of target features surrounding the target edge is determined. Using the geometric information as input, the ML model generates SRAFs to be placed around the target edge.
Abstract:
A method including: obtaining a thin-mask transmission function of a patterning device and a M3D model for a lithographic process, wherein the thin-mask transmission function represents a continuous transmission mask and the M3D model at least represents a portion of M3D attributable to multiple edges of structures on the patterning device; determining a M3D mask transmission function of the patterning device by using the thin-mask transmission function and the M3D model; and determining an aerial image produced by the patterning device and the lithographic process, by using the M3D mask transmission function.
Abstract:
A method for determining an image of a mask pattern in a resist coated on a substrate, the method including determining an aerial image of the mask pattern at substrate level; and convolving the aerial image with at least two orthogonal convolution kernels to determine a resist image that is representative of the mask pattern in the resist.
Abstract:
A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.
Abstract:
The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.
Abstract:
Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.
Abstract:
The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.
Abstract:
A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.
Abstract:
Methods of generating a characteristic pattern for a patterning process and training a machine learning model. A method of training a machine learning model configured to generate a characteristic pattern for a mask pattern includes obtaining (i) a reference characteristic pattern that meets a satisfactory threshold related to manufacturing of the mask pattern, and (ii) a continuous transmission mask (CTM) for use in generating the mask pattern; and training, based on the reference characteristic pattern and the CTM, the machine learning model such that a first metric between the characteristic pattern and the CTM, and a second metric between the characteristic pattern and the reference characteristic pattern is reduced.
Abstract:
The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.