公开(公告)号：US08171626B1

公开(公告)日：2012-05-08

申请号：US13155375

申请日：2011-06-07

Applicant: Cheng-Po Yu ,  Chi-Min Chang

Inventor： Cheng-Po Yu ,  Chi-Min Chang

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

CPC classification number: H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

Abstract translation: 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

公开(公告)号：US20070281388A1

公开(公告)日：2007-12-06

申请号：US11456213

申请日：2006-07-10

Applicant: Cheng-Po Yu ,  Cheng-Hung Yu ,  Chi-Min Chang

Inventor： Cheng-Po Yu ,  Cheng-Hung Yu ,  Chi-Min Chang

IPC: H01L21/00 ,  H01L21/4763

CPC classification number: H05K3/243 ,  H01L21/6715 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/28 ,  H05K2201/0391 ,  H05K2203/013 ,  H05K2203/058

Abstract: A selective metal surface treatment process of a circuit board, which has a solder mask and a multiple of selective metal treatment surface areas, wherein the solder mask covers the surface of the circuit board but exposes the selective metal surface treatment areas, is provided. The selective metal surface treatment process includes using a printhead to selectively print a resist on a selective metal surface treatment area, performing a surface treatment of the other selective metal surface treatment areas, and removing the resist. A selective metal surface treatment apparatus used for performing the selective metal surface treatment process of the circuit board is also provided. Through the present invention, unnecessary waste of the materials in the process is reduced and the processing time is shortened.

Abstract translation: 提供具有焊接掩模和多个选择性金属处理表面积的电路板的选择性金属表面处理工艺，其中焊接掩模覆盖电路板的表面，但暴露选择性金属表面处理区域。 选择性金属表面处理方法包括使用打印头选择性地在选择性金属表面处理区域上印刷抗蚀剂，对其它选择性金属表面处理区域进行表面处理，并除去抗蚀剂。 还提供了用于执行电路板的选择性金属表面处理工艺的选择性金属表面处理装置。 通过本发明，可以减少处理过程中不必要的材料浪费，缩短处理时间。

公开(公告)号：US20110094778A1

公开(公告)日：2011-04-28

申请号：US12606192

申请日：2009-10-27

Applicant: Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

Inventor： Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

IPC: H05K1/00 ,  B23K26/38

CPC classification number: H05K3/185 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0236

Abstract: A method for fabricating a circuit board is provided. A non-conductive material layer is provided on a core substrate, wherein the non-conductive material layer comprises a dielectric material and catalytic particles. A recessed circuit structure is then formed in the non-conductive material layer with a laser beam. Simultaneously, the catalytic particles in the recessed circuit structure are activated with aid of the laser. A buried conductive structure is then formed in the recessed circuit structure by chemical copper deposition methods.

Abstract translation: 提供一种制造电路板的方法。 非导电材料层设置在芯基板上，其中非导电材料层包括电介质材料和催化颗粒。 然后在非导电材料层中用激光束形成凹陷的电路结构。 同时，凹陷电路结构中的催化颗粒借助于激光器被激活。 然后通过化学铜沉积方法在凹陷电路结构中形成掩埋导电结构。

公开(公告)号：US20070263862A1

公开(公告)日：2007-11-15

申请号：US11465814

申请日：2006-08-21

Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Chi-Min Chang ,  Cheng-Hung Yu

Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Chi-Min Chang ,  Cheng-Hung Yu

IPC: G09C3/08

CPC classification number: H05K1/0269 ,  H05K3/0097 ,  H05K3/225 ,  H05K2201/09936 ,  H05K2203/013

Abstract: A manufacturing process and an apparatus for printing imprint on defective board are provided. An automatic printing device is used for replacing operator, so as to reduce manpower and to increase the correctness and veracity of defect mark printing. The manufacturing process includes the following steps: first, an image sensor captures an image of a defect mark and transmits the image to a processing unit for data processing. Next, the data is compared, and an inkjet head is notified of the correct printing position to print ink on the customer identification mark of the printed circuit board.

Abstract translation: 提供了制造工艺和用于在缺陷板上印刷压印的装置。 使用自动打印装置来代替操作者，以减少人力和提高缺陷标记打印的正确性和真实性。 制造过程包括以下步骤：首先，图像传感器捕获缺陷标记的图像，并将图像发送到用于数据处理的处理单元。 接下来，比较数据，并且通知喷墨头正确的打印位置以在印刷电路板的客户识别标记上印刷墨水。

公开(公告)号：US08987608B2

公开(公告)日：2015-03-24

申请号：US13615722

申请日：2012-09-14

Applicant: Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

Inventor： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

公开(公告)号：US08598463B2

公开(公告)日：2013-12-03

申请号：US13050009

申请日：2011-03-17

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/00 ,  C23C18/16

CPC classification number: H05K3/12 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/022 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/02 ,  H05K3/181 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/0187 ,  Y10T29/302 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract translation: 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。

公开(公告)号：US08373071B2

公开(公告)日：2013-02-12

申请号：US12696629

申请日：2010-01-29

Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

IPC: H05K1/00

CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层，其中活化绝缘层包括多个催化剂颗粒，并覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

公开(公告)号：US20120031651A1

公开(公告)日：2012-02-09

申请号：US12944275

申请日：2010-11-11

Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

Abstract: A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

Abstract translation: 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。

公开(公告)号：US07867908B2

公开(公告)日：2011-01-11

申请号：US12422428

申请日：2009-04-13

Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

IPC: H01L21/302

CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

公开(公告)号：US07834274B2

公开(公告)日：2010-11-16

申请号：US11554882

申请日：2006-10-31

Applicant: Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K1/03

CPC classification number: H05K3/182 ,  H05K3/389 ,  H05K3/421 ,  H05K3/422 ,  H05K3/426 ,  H05K3/4661 ,  H05K2203/013 ,  H05K2203/0565 ,  H05K2203/0709 ,  Y10T29/49155

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成 在所述第一SAM上形成非粘性膜，在所述基底中形成至少一个微孔，在所述微孔的表面上形成第二SAM，在所述基底的至少一侧和所述微孔的表面上提供催化剂颗粒，以及 在基板上形成催化剂电路图案。