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公开(公告)号：DE2716520A1
公开(公告)日：1977-11-10
申请号：DE2716520
申请日：1977-04-14
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , DAVIS MICHAEL IAN , HOOD ROBERT ALLEN , GRAYBIEL LYNN ALLAN , BOCA RATON FLA , KAHN SAMUEL , OSBORNE WILLIAM STEESE , BOURKE DONALL GARRAID , PUTTLITZ FREDERIC JOHN
Abstract: The look ahead circuits are for an address relocation translator which contains stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive look ahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation the loaded look ahead bits are outgated while the block address is being read from an SR. The look ahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The look ahead bits are handled by parallel high speed circuits so that the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.
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公开(公告)号：CH615521A5
公开(公告)日：1980-01-31
申请号：CH527477
申请日：1977-04-28
Applicant: IBM
Inventor： BOURKE DONALL GARRAID , PUTTLITZ FREDERIC JOHN
Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.
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公开(公告)号：AU2475077A
公开(公告)日：1978-11-09
申请号：AU2475077
申请日：1977-05-02
Applicant: IBM
Inventor： BOURKE DONALL GARRAID , PUTTLITZ FREDERIC JOHN
Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.
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