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    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR
    1.
    发明申请
    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
    非自对准信号异相双极晶体管

    公开(公告)号：WO03001584A8

    公开(公告)日：2004-05-27

    申请号：PCT/US0219789

    申请日：2002-06-19

    Applicant: IBM

    Inventor： JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B ,  JOHNSON ROBB A ,  LANZEROTTI LOUIS D ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

    IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L31/11

    CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

    Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

    Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

    METHOD FOR MANUFACTURING HETEROJUNCTION BI-POLAR TRANSISTOR
    3.
    发明专利
    METHOD FOR MANUFACTURING HETEROJUNCTION BI-POLAR TRANSISTOR 审中-公开

    公开(公告)号：JP2002324805A

    公开(公告)日：2002-11-08

    申请号：JP2002068969

    申请日：2002-03-13

    Applicant: IBM

    Inventor： JAGANNATHAN BASANTH

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To disclose a method for manufacturing a heterojunction bi-polar transistor having a collector, base, and emitter regions. SOLUTION: The method of this invention includes a step of forming a silicon epitaxial layer that defines the collector region on a substrate. An oxide layer is formed on the silicon epitaxial layer, then a nitride layer is formed on a stacked oxide layers. Subsequently, an emitter opening is defined inside the nitride layer, and then a base cavity is formed inside the stacked oxide layers. The base cavity extends in the transverse direction across a width of the emitter opening. A silicon germanium Epitaxial layer is grown defining the base region inside the base cavity. Finally, a poly-silicon layer defining the emitter region is deposited on the silicon germanium Epitaxial layer.

    INTEGRATION SYSTEM OF BiCMOS HAVING RAISED EXTERNAL BASE
    5.
    发明专利
    INTEGRATION SYSTEM OF BiCMOS HAVING RAISED EXTERNAL BASE 有权
    带有外部基底的BiCMOS集成系统

    公开(公告)号：JP2004319983A

    公开(公告)日：2004-11-11

    申请号：JP2004085745

    申请日：2004-03-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

    IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

    CPC classification number: H01L21/8249 ,  H01L27/0623

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
    SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

    STEPPED COLLECTOR IMPLANTATION AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明专利
    STEPPED COLLECTOR IMPLANTATION AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：JP2002324806A

    公开(公告)日：2002-11-08

    申请号：JP2002075491

    申请日：2002-03-19

    Applicant: IBM

    Inventor： FREEMAN GREGORY G ,  JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/36 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To provide an element structure and a method for manufacturing the same for suppressing an increase of an unnecessary capacitance in the element as small as possible and for improving a transistor characteristic. SOLUTION: In an integrated bi-polar circuit element, a stepped collector dopant profile reduces a transit time and a parasitic capacitance between an emitter and a collector due to a minimum increase of the parasitic capacitance. A shallow implantation reduces a width of a space charge region between a base and the collector, reduces a resistance, and individually optimizes a breakdown characteristic between the collector and the base. A deep implantation, then, links a buried collector to a sub-collector and provides a low resistance path to the sub-collector. The stepped collector dopant profile only gives the lowest effect against a capacitance the collector and the base outside an intrinsic region of the element. The reason is that the higher concentration dopant is compensated by an exogenous dopant outside the intrinsic region or is buried therein.

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