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    Instruction group formation and mechanism for smt dispatch
    1.
    发明专利
    Instruction group formation and mechanism for smt dispatch 审中-公开
    SMT贴片的指令组形成和机制

    公开(公告)号：JP2006114036A

    公开(公告)日：2006-04-27

    申请号：JP2005294193

    申请日：2005-10-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CURRAN BRIAN WILLIAM ,  KONIGSBURG BRIAN R ,  HUNG QUI LE ,  ARNOLD LUICK DAVID ,  NGUYEN DUNG QUOC

    IPC: G06F9/46 ,  G06F9/38

    CPC classification number: G06F9/3853 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3885

    Abstract: PROBLEM TO BE SOLVED: To simultaneously execute a plurality of instructions, and thereby efficiently use hardware resources to increase the whole processor throughput.
    SOLUTION: A resource vector representing a necessary resource is encoded to a resource field, and the resource field is decoded in the subsequent step in order to derive the resource vector. The resource field is stored in an instruction cache related to respective program instructions. A processor operates in a simultaneous multithreading mode. When validity of a resource is equal to or exceeds a resource requirement of an instruction group, instructions thereof are simultaneously dispatched to hardware resources. A starting bit is inserted into one of the program instructions in order to define the instruction group. The hardware resource is, in particular, an execution unit such as a fixed decimal point unit 56, a load/store unit 58, a floating decimal point unit 60 or a branch processing unit 61.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：同时执行多个指令，从而有效地使用硬件资源来增加整个处理器的吞吐量。 解决方案：将表示必要资源的资源向量编码到资源字段，并且在后续步骤中对资源字段进行解码，以便导出资源向量。 资源字段存储在与各个程序指令相关的指令高速缓存中。 处理器以同时多线程模式运行。 当资源的有效性等于或超过指令组的资源需求时，其指令被同时发送到硬件资源。 为了定义指令组，将起始位插入其中一个程序指令。 硬件资源特别是诸如固定小数点单元56，加载/存储单元58，浮动小数点单元60或分支处理单元61之类的执行单元。（C）2006， JPO＆NCIPI

    3.
    发明专利
    未知

    公开(公告)号：DE69120878D1

    公开(公告)日：1996-08-22

    申请号：DE69120878

    申请日：1991-08-09

    Applicant: IBM

    Inventor： CURRAN BRIAN WILLIAM

    IPC: G06F12/02 ,  G11C8/00 ,  G11C11/401 ,  G11C11/408

    Abstract: Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access. The main memory hardware redrives that row address to the DRAMs after completion of an access, and the memory controller compares each new row address with the row address of the last access, allowing the DRAM to be accessed immediately if the two addresses are the same by activating the Row Address Strobe (RAS).

    4.
    发明专利
    未知

    公开(公告)号：DE68924313D1

    公开(公告)日：1995-10-26

    申请号：DE68924313

    申请日：1989-06-20

    Applicant: IBM

    Inventor： CURRAN BRIAN WILLIAM ,  D ONOFRIO JOSEPH MICHAEL ,  FUQUA RICHARD NICKELS ,  HERZL ROBERT DOV ,  MILICH LOUIS JAMES ,  MOORE PAUL MILTON ,  TEMPLE JOSEPH LESTER

    IPC: G06F12/08 ,  G06F15/16

    Abstract: An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

    6.
    发明专利
    未知

    公开(公告)号：DE68924313T2

    公开(公告)日：1996-05-02

    申请号：DE68924313

    申请日：1989-06-20

    Applicant: IBM

    Inventor： CURRAN BRIAN WILLIAM ,  D ONOFRIO JOSEPH MICHAEL ,  FUQUA RICHARD NICKELS ,  HERZL ROBERT DOV ,  MILICH LOUIS JAMES ,  MOORE PAUL MILTON ,  TEMPLE JOSEPH LESTER

    IPC: G06F12/08 ,  G06F15/16

    Abstract: An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

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