公开(公告)号：US3583918A

公开(公告)日：1971-06-08

申请号：US3583918D

申请日：1968-05-14

Applicant: IBM

Inventor： TURNBULL ROBERT C ,  DAM REYNIER W ,  DUBETSKY DERRY J

IPC: C04B35/26 ,  C04B35/36

CPC classification number: C04B35/2616

Abstract: A FAST SWITCHING, SQUARE LOOP, TEMPERATURE STABLE, FERRITE CORE, SUITABLE FOR COMPUTER APPLICATIONS IS PROVIDED. THE COMPOSITION CONSISTS OF THE OXIDES OR CARBONATES OR THE LIKE OF LITHIUM, COPPER, MANGANESE AND IRON IN PREDETERMINED PROPORTIONS. THE COMPONENTS ARE MIXED SHAPED, FIRED AND QUENCHED TO OBTAIN THE STORAGE CORE OF THE DESIRED PROPERTIES.

公开(公告)号：CA1129268A

公开(公告)日：1982-08-10

申请号：CA361714

申请日：1980-10-07

Applicant: IBM

Inventor： DUBETSKY DERRY J

IPC: B28B1/30 ,  C04B35/64 ,  C04B41/80 ,  C04B41/81 ,  F27D3/12 ,  H05K1/03 ,  H05K3/46 ,  C04B33/32 ,  F27D5/00

Abstract: A method of achieving uniform shrinkage of a laminated green ceramic substrate during sintering wherein the substrate is placed on a flat, relatively thick plate of refractory material such as molybdenum, tantalum or tungsten or alloys thereof with the flat plate provided with a thin surface coating layer of a ceramic material, and heating the substrate to a sintering temperature and maintaining the temperature for a time sufficient to sinter the substrate. A setter plate for supporting a planar green ceramic substrate during the sinterinq operation, the setter plate is made of a refractory material and provided with a thin ceramic coating at least on the top surface.

公开(公告)号：CA1286791C

公开(公告)日：1991-07-23

申请号：CA589395

申请日：1989-01-27

Applicant: IBM

Inventor： BOSS DAVID W ,  CARR TIMOTHY W ,  DUBETSKY DERRY J ,  GREENSTEIN GEORGE M ,  GROBMAN WARREN D ,  HAYUNGA CARL P ,  KUMAR ANANDA H ,  LANGE WALTER F ,  MASSEY ROBERT H ,  PALMATEER PAUL H ,  ROMANO JOHN A ,  SHIH DA-YUAN

IPC: H05K9/00 ,  H01L23/498 ,  H05K3/46 ,  H01L23/485

Abstract: Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymeric overlayers with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.

公开(公告)号：CA1232978A

公开(公告)日：1988-02-16

申请号：CA501733

申请日：1986-02-12

Applicant: IBM

Inventor： BOSS DAVID W ,  DUBETSKY DERRY J

IPC: H01L23/538 ,  C04B35/64 ,  H01L21/48 ,  H01L23/52 ,  H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00 ,  H05K3/46 ,  H01L27/04 ,  H01L21/72

Abstract: Process For Minimizing Distortion In Multilayer Ceramic Substrates A method of fabricating a multilayer ceramic substrate with an internal conductive metallurgy circuit network, wherein additional green sheet material is added to the stack of ceramic green sheets during assembly to areas of the substrate outside of the conductive metallurgy to compensate for the volume of conductive metal paste to thereby eliminate or minimize substrate distortion during the sintering operation. FI9-85-002