公开(公告)号：WO2012058011A3

公开(公告)日：2012-06-14

申请号：PCT/US2011056119

申请日：2011-10-13

Applicant: IBM ,  FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

Inventor： FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure including a dielectric layer (202) having a conductive feature (204) embedded therein, the conductive feature (204) having a first top surface (208) that is substantially coplanar with a second top surface (206) of the dielectric layer (202); a metal cap layer (212) located directly on the first top surface (208), wherein the metal cap layer (212) does not substantially extend onto the second top surface (206); a first dielectric cap layer (21 0A) located directly on the second top surface (206), wherein the first dielectric cap layer (21 0A) does not substantially extend onto the first top surface (208) and the first dielectric cap layer (210A) is thicker than the metal cap layer (212); and a second dielectric cap layer (220) on the metal cap layer (212) and the first dielectric cap layer (210A). A method of forming the interconnect structure is also provided.

Abstract translation: 一种改进的互连结构，包括具有嵌入其中的导电部件（204）的电介质层（202），所述导电部件（204）具有与电介质的第二顶表面（206）基本共面的第一顶表面 层（202）; 直接位于所述第一顶面（208）上的金属盖层（212），其中所述金属盖层（212）基本上不延伸到所述第二顶面（206）上; 直接位于第二顶表面（206）上的第一电介质盖层（210A），其中第一电介质盖层（210A）基本上不延伸到第一顶表面（208）上并且第一电介质盖层（210A） ）比金属盖层（212）厚; 和在金属盖层（212）和第一电介质盖层（210A）上的第二电介质盖层（220）。 还提供了形成互连结构的方法。

公开(公告)号：DE69020796D1

公开(公告)日：1995-08-17

申请号：DE69020796

申请日：1990-04-09

Applicant: IBM

Inventor： APPEL BERND K ,  BINDRA PERMINDER ,  EDWARDS ROBERT D ,  LOOMIS JAMES R ,  PARK JOE M ,  REID JONATHAN D ,  SMITH LISA J ,  WHITE JAMES R

IPC: C25D5/56 ,  H05K3/42

公开(公告)号：DE69020796T2

公开(公告)日：1996-03-14

申请号：DE69020796

申请日：1990-04-09

Applicant: IBM

Inventor： APPEL BERND K ,  BINDRA PERMINDER ,  EDWARDS ROBERT D ,  LOOMIS JAMES R ,  PARK JOE M ,  REID JONATHAN D ,  SMITH LISA J ,  WHITE JAMES R

IPC: C25D5/56 ,  H05K3/42

公开(公告)号：CA2110472A1

公开(公告)日：1994-09-02

申请号：CA2110472

申请日：1993-12-01

Applicant: IBM

Inventor： BHATT ANILKUMAR C ,  BUDA LEO R ,  EDWARDS ROBERT D ,  HART PAUL J ,  INGRAHAM ANTHONY P ,  MARKOVICH VOYA R ,  MOLLA JAYNAL A ,  MURPHY RICHARD G ,  SAXENMEYER GEORGE J JR ,  WALKER GEORGE F ,  WHALEN BETTE J ,  ZARR RICHARD S

IPC: G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  G01R31/26

Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.