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公开(公告)号:GB2600338A
公开(公告)日:2022-04-27
申请号:GB202201027
申请日:2020-07-03
Applicant: IBM
Inventor: STUART SIEG , DANIEL JAMES DECHENE , ERIC MILLER
IPC: H01L21/02
Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.
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公开(公告)号:GB2556224B
公开(公告)日:2019-10-30
申请号:GB201720310
申请日:2016-05-06
Applicant: IBM
Inventor: SIVANANDA KANAKASABAPATHY , FEE LI LIE , GAURI KARVE , SOON-CHEON SEO , STUART SIEG , HONG HE , DERRICK LIU , BRUCE DORIS
IPC: H01L21/336 , H01L29/78
Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
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公开(公告)号:GB2556224A
公开(公告)日:2018-05-23
申请号:GB201720310
申请日:2016-05-06
Applicant: IBM
Inventor: SIVANANDA KANAKASABAPATHY , FEE LI LIE , GAURI KARVE , SOON-CHEON SEO , STUART SIEG , HONG HE , DERRICK LIU , BRUCE DORIS
Abstract: A semiconductor structure is provided that includes a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) straddles a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P/50P) is located on opposing sidewall surfaces of the gate structure (16L/16R); and a second set of gate spacers (32P) is located on sidewalls of the first set of gate spacers (24P/50P). One gate spacer of the second set of spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).
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