公开(公告)号：GB2577417B

公开(公告)日：2021-09-08

申请号：GB201917399

申请日：2018-05-10

Applicant: IBM

Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

IPC: H01L27/04

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：GB2577417A

公开(公告)日：2020-03-25

申请号：GB201917399

申请日：2018-05-10

Applicant: IBM

Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

IPC: H01L27/04

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：GB2556224B

公开(公告)日：2019-10-30

申请号：GB201720310

申请日：2016-05-06

Applicant: IBM

Inventor： SIVANANDA KANAKASABAPATHY ,  FEE LI LIE ,  GAURI KARVE ,  SOON-CHEON SEO ,  STUART SIEG ,  HONG HE ,  DERRICK LIU ,  BRUCE DORIS

IPC: H01L21/336 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：GB2556224A

公开(公告)日：2018-05-23

申请号：GB201720310

申请日：2016-05-06

Applicant: IBM

Inventor： SIVANANDA KANAKASABAPATHY ,  FEE LI LIE ,  GAURI KARVE ,  SOON-CHEON SEO ,  STUART SIEG ,  HONG HE ,  DERRICK LIU ,  BRUCE DORIS

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) straddles a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P/50P) is located on opposing sidewall surfaces of the gate structure (16L/16R); and a second set of gate spacers (32P) is located on sidewalls of the first set of gate spacers (24P/50P). One gate spacer of the second set of spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).