公开(公告)号：DE3071732D1

公开(公告)日：1986-10-09

申请号：DE3071732

申请日：1980-03-20

Applicant: IBM

Inventor： HO CHUNG WEN

IPC: H01L23/12 ,  H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H01L23/54

Abstract: A module (9) for LSI chips includes an orthogonal array of sets of pads and fan-out metallization (11) for a large number of chips (10). Running parallel to the sides of the chips and the fan-out area are several parallel discrete, prefabricated, thin film engineering change interconnection lines (15, 28) terminating in pads adjacent to the fan-out. The pads are arranged to permit discretionary connections of the fan-out pads (12) to the engineering change pads (14) with minimal crossovers by means of short fly wires (13, 17, 21, 25). A staggered pad arrangement minimizes potential crossovers and maximizes the number of interconnection lines that can be fabricated.

公开(公告)号：DE3177003D1

公开(公告)日：1989-04-13

申请号：DE3177003

申请日：1981-06-03

Applicant: IBM

Inventor： BAJOREK CHRISTOPHER HENRY ,  CHANCE DUDLEY AUGUSTUS ,  HO CHUNG WEN ,  THOMPSON DAVID ALLEN

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/64 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46 ,  H05K3/36 ,  H01G4/30 ,  H01L23/12 ,  H01L23/56

Abstract: A carrier for microcircuit LSI chips (180) includes stacks (11) of parallel ceramic sheets (14) carrying thin conductive capacitor plates (20) laminated in a ceramic structure, in which the capacitor plates serve as power distribution conductors. Groups of plates provide electrical connection (19,21) beteeen power supply strips (16) and conductor straps (95, 98) which are connected to solder bonds (181) for the chips. This provides capacitance to smooth the power supply to high switching speed VSL1 chips. Stacks (11) of laminated ceramic capacitors serving as power planes are inserted into slots in laminated ceramic sheets. Signal vias (42) are provided about the periphery of the power planes. A highly parallel distribution of current is provided by means of horizontal power conducting straps which reduce voltage fluctuations, electrical resistance, and current per via.

公开(公告)号：DE2920564A1

公开(公告)日：1980-01-10

申请号：DE2920564

申请日：1979-05-21

Applicant: IBM

Inventor： HO CHUNG WEN

IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/52 ,  H01L23/538 ,  H01L23/64 ,  H01L23/66 ,  H01P1/22 ,  H01P3/08 ,  H01L49/02

公开(公告)号：DE3676832D1

公开(公告)日：1991-02-21

申请号：DE3676832

申请日：1986-02-07

Applicant: IBM

Inventor： BLAKESLEE MARYBELLE C ,  CHANCE DUDLEY AUGUSTUS ,  EASTMAN DEAN ERIC ,  GNIEWEK JOHN J ,  HO CHUNG WEN ,  LEVINE ERNEST N ,  ORDONEZ JOSE E ,  REILEY TIMOTHY CLARK ,  SKARVINKO EUGENE R

IPC: H01L21/60 ,  H01L23/498 ,  H05K1/03 ,  H05K3/34 ,  H05K3/40

公开(公告)号：DE3276982D1

公开(公告)日：1987-09-17

申请号：DE3276982

申请日：1982-11-05

Applicant: IBM

Inventor： CHANCE DUDLEY AUGUSTUS ,  PLATT ALAN ,  HO CHUNG WEN ,  RAY SUDIPTA KUMAR

IPC: H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K3/22

Abstract: A chip carrying module includes a number of engineering change lines (ECX, ECY) buried below the surface of the module. The engineering change lines are interrupted periodically to provide a set of vias (48, 84; 49, 53; 54, 58) extending up to the upper surface of the module between each set of chips (10-15) where the vias are connected by dumbbell-shaped pads (45-47, 50-52, 55-57) including a narrow link (46, 51, 56) which permits laser deletion or the like. In addition, the dumbbell-shaped pads are located adjacent to the fan-out pads (41, 75) for the chips. Thus, the fan-out pads can be connected to the dumbbell-shaped pads (45, 70) by means of fly-wires (44, 74). In addition, individual engineering change lines can be connected together to reach every region of the module by connecting a fly-wire (59) from one dumbbell-shaped pad (55) to another (60). In addition, by deleting the links (46, 56, 83, 71) at such dumbbell-shaped pads, the engineering change connections are limited to the particular path required.

公开(公告)号：DE3376913D1

公开(公告)日：1988-07-07

申请号：DE3376913

申请日：1983-08-31

Applicant: IBM

Inventor： CHANCE DUDLEY AUGUSTUS ,  HO CHUNG WEN ,  REILEY TIMOTHY CLARK

IPC: H01G2/06 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K3/34 ,  H01G1/035 ,  H01G1/147

公开(公告)号：DE3166953D1

公开(公告)日：1984-12-06

申请号：DE3166953

申请日：1981-07-21

Applicant: IBM

Inventor： BAJOREK CHRISTOPHER HENRY ,  CHANCE DUDLEY AUGUSTUS ,  HO CHUNG WEN

IPC: H01L23/12 ,  H01G4/12 ,  H01G4/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L27/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46 ,  H05K3/00 ,  H01G4/40

Abstract: A laminated ceramic sheet printed circuit carrier (1) for supporting semiconductor integrated circuit chips (11) has a coefficient of thermal expansion matched to that of the chips (11) as well as a high value of capacitance. The carrier (1) provides both mechanical and electrical connections to the chip (11). The carrier (1) contains a matrix of dot capacitors (9) formed between laminated layers (2) of ceramic material. In some cases, conductive layers are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets. … In addition to its principal application in a chip carrier, other applications are in chip interposers and discrete capacitors for mounting on chip carriers.