公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

公开(公告)号：SG92715A1

公开(公告)日：2002-11-19

申请号：SG200003551

申请日：2000-06-24

Applicant: IBM

Inventor： JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

Abstract: A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

公开(公告)号：SG106602A1

公开(公告)日：2004-10-29

申请号：SG200100992

申请日：2001-02-21

Applicant: IBM

Inventor： GERALD G ADVOCATE JR ,  FRANCIS J DOWNES JR ,  LUIS J MATIENZO ,  RONALD A KASCHAK ,  JOHN STEVEN KRESGE ,  DANIEL C VAN HART

IPC: C23C18/18 ,  C25D7/00 ,  H01L21/60 ,  H01L23/498 ,  H01L23/522 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/06 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/461 ,  H01L23/52

公开(公告)号：SG91857A1

公开(公告)日：2002-10-15

申请号：SG200001280

申请日：2000-03-09

Applicant: IBM

Inventor： ERIC A JOHNSON ,  JOHN STEVEN KRESGE

IPC: H01L23/28 ,  H01L23/12 ,  H01L23/32 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01L23/485

Abstract: A method and structure for reducing thermally induced strains on the solder joints that couple a ball grid array (BGA) module to a circuit card, so as to improve the fatigue life of the BGA module. The thermally induced strains arise from a mismatch in thermal expansion coefficient between the dielectric substrate of the BGA module and the dielectric board of the circuit card. The method generates void annular regions around portions of the BGA dielectric substrate to which the BGA solder balls are to be attached and/or around portions of the circuit card dielectric material to which the BGA module is to be attached. This results in the formation of dielectric islands or peninsulas that bound the solder balls of the BGA module after installation on the circuit card. The dielectric islands or peninsulas thus formed serve to increase the effective height over which the differential expansion is accommodated, thereby reducing the strains throughout the solder joints. Additionally, the void annular regions provide space for the deformation of the dielectric islands or peninsulas, thereby increasing their compliance and transferring strain from the solder joints to the dielectric islands or peninsulas.