公开(公告)号：MY125420A

公开(公告)日：2006-07-31

申请号：MYPI20001268

申请日：2000-03-29

Applicant: IBM

Inventor： ROBERT M JAPP ,  MARK D POLIKS

IPC: H05K1/02 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

Abstract: POWER AND GROUND PLANES THAT ARE USED IN PRINTED CIRCUIT BOARDS (PCBS) AND THAT COMPRISE POROUS, CONDUCTIVE MATERIALS ARE DISCLOSED. USING POROUS POER AND GROUND PLANE MATERIALS IN PCBS ALLOWS LIQUIDS (E.G., WATER AND/OR OTHER SOLVENTS) TO PASS THROUGH THE POWER AND GROUNDS PLANES, THUS DECREASING FAILURES IN PCBS (OR PCBS USED AS LAMINATE CHIP CARRIERS) CAUSED BY CATHODIC/ ANODIC FILAMENT GROWTH AND DELAMATION OF INSULATORS. POROUS CONDUCTIVE MATERIALS SUITABLE FOR USE IN PCBS MAY BE FORMED BY USING METAL COATED ORGANIC CLOTHS (SUCH AS POLYSTER ORLIQUID CRYSTAL POLYMERS) OR FABRICS (SUCH AS THOSE MADE FROM CARBON/GRAPHITE OR GLASS FIBERS), USING METAL WIRE MESH INSTEAD OF METAL SHEETS, USING SINTERED METAL, OR MAKING METAL SHEETS POROUS BY FORMING AN ARRAY OF HOLES IN THE METAL SHEETS. FABRICS AND MESH MAY BE WOVEN OR RANDOM. IF AN ARRAY OF HOLED IS FORMED IN A METAL SHEET, SUCH AN ARRAY MAY BE FORMED WITH NO ADDITIONAL PROCESSING STEPS THAN ARE PERFORMED USING CONVENTIONAL PCB ASSEMBLY METHODS.(FIG.1)

公开(公告)号：SG97874A1

公开(公告)日：2003-08-20

申请号：SG200001741

申请日：2000-03-24

Applicant: IBM

Inventor： ROBERT M JAPP ,  MARK D POLIKS

IPC: H05K1/03 ,  H05K3/46

Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.

公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.