公开(公告)号：JPH11315384A

公开(公告)日：1999-11-16

申请号：JP3487499

申请日：1999-02-12

Applicant: IBM

Inventor： DAVID JOHN RUSSELL ,  GERALD WALTER JONES ,  HEIKE MARCELLO ,  BOYA RISTA MARKOVICH

IPC: C23C18/18 ,  C23C18/31 ,  G03F7/038 ,  H05K3/00 ,  H05K3/18 ,  H05K3/24 ,  H05K3/28

Abstract: PROBLEM TO BE SOLVED: To provide a method for selectively applying electroless plating of metal, particularly gold and copper on a substrate such as a circuited substrate. SOLUTION: This method contains a stage in which the surface of a substrate 12 is applied with a dielectric permanent plating resist 16 contg. about 10 to 80% phenoxypolyol resin of about 40,000 to 130,000 molecular weight which is a condensate of epichloro-hydrin and bisphenol A, about 20 to 90% epoxidated multifunctional bisphenol A-formaldehyde-novolak resin of about 4,000 to 10,000 molecular weight, about 35 to 50% diglycidyl-ether of bisphenol A of about 600 to 2,500 and a cationic photoinitiator and capable of photoimaging by curing, a stage in which the permanent plating resist 16 is photopatterned, and the opening 18 exposing the region of the substrate 12 is formed therein and a stage in which the exposed region of the substrate 12 is applied with electroless plating of metal.

公开(公告)号：JPH11289164A

公开(公告)日：1999-10-19

申请号：JP9499

申请日：1999-01-04

Applicant: IBM

Inventor： GERALD WALTER JONES ,  ROSS WILLIAM KIESLER ,  BOYER LISTA MARKOVICH ,  WILLIAM JOHN LUDICK ,  WILSON JAMES W ,  WILLIAM R WILSON

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/16 ,  H05K3/38 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a circuit structure comprising lamination and a plurality of internal flat surfaces of high wiring-density. SOLUTION: A method of manufacturing a circuit structure comprises a step, where an organic substrate 12 comprising a circuit 14 over it is provided, a step for coating a dielectric film 30 on the organic substrate 12, a step for forming a micro via in the dielectric film 30, a step for sputtering a metal seed layer 20 on the dielectric film 30 and in the micro via, a step for placing a metal layer 22 on the metal seed layer 20, and a step for forming a circuit pattern over it.

公开(公告)号：JPH1092977A

公开(公告)日：1998-04-10

申请号：JP21839897

申请日：1997-08-13

Applicant: IBM

Inventor： ANASTASIOS PETEL ANGEROPUUROSU ,  GERALD WALTER JONES ,  RICHARD WILLIAM MAREKU ,  HAIKE MARUTSUERO ,  JEFFREY MATSUKEBUINII

IPC: C08L63/04 ,  H01L23/14 ,  H05K3/18

Abstract: PROBLEM TO BE SOLVED: To manufacture an electronic package having an organic board. SOLUTION: An electronic package board is made of glass fibers and epoxy resin. In order to form a circuit on the electronic package board by an additive method, organic polymer electrolyte is applied to the surface of the organic board. A colloidal palladium-tin seed layer is deposited on the surface of the organic polymer electrolyte. Successively, optically focusable polymer is applied to the surface of the seed layer. The optically focusable polymer layer is patterned by photolithography to expose a part of the seed layer. The exposed part of the seed layer functions as catalyst of nonelectrolytic copper plating. Thus, a copper conductor layer is applied to the exposed part of the seed layer. In accordance with the ionization characteristics of employed individual polymer electrolytes, the organic polymer electrolyte is deposited from a solution whose pH is suitable for the required seed catalyst covering.

公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.